Patent application number | Description | Published |
20090298680 | ALUMINUM PRODUCT AND METHOD FOR PRODUCING SAME - An aluminum product includes an aluminum substrate, a porous alumina film formed on the aluminum substrate, and a photo-catalyst film. The alumina film has an array of pores defined on a surface thereof. The photo-catalyst film is formed on the surface of the alumina film and inner walls of the alumina film located in the pores. An exemplary method for producing the aluminum product is also provided. | 12-03-2009 |
20100045979 | PHOTOCATALYSIS TESTING DEVICE - A photocatalysis testing device includes a reaction chamber, a light source, and a spectrophotometer. Reactants including a methylene blue (MB) solution and a photocatalyst can be added to the reaction chamber and illuminated by the light source. Color vanishing rate of the MB solution can be measured by the spectrophotometer. Further, the photocatalysis testing device also includes a light-tight chamber and a temperature stabilizer. The reaction chamber and the light source are received in the light-tight chamber to avoid ambient light effecting on the photocatalysis test. The spectrophotometer is positioned outside the light-tight chamber and optically coupled to the reaction chamber. The temperature stabilizer is configured for stabilizing temperature of the MB solution. | 02-25-2010 |
20100071618 | FILM COATING HOLDER AND FILM COATING DEVICE USING SAME - A film coating device for coating a flexible substrate includes a housing and a film coating holder for holding the flexible substrate. The housing defines a chamber, and the film coating holder is received in the chamber. The film coating holder includes a motor, a driving roller, and a driven roller. The driving roller is rotatable by a motor relative to the housing. The driven roller is substantially parallel to the driving roller. The driven roller is rotatable together with the driving roller by transmission of the flexible substrate. | 03-25-2010 |
20100151271 | MULTILAYER SUBSTRATE - A multilayer substrate includes a base layer, a coating layer and an intermediate layer positioned between the base layer and the coating layer. The intermediate layer contains chromium and nitrogen. A content of the chromium in the intermediate layer gradually decreases from the base layer to the coating layer. | 06-17-2010 |
20110030614 | WET COATING SYSTEM HAVING ANNEALING CHAMBER - An exemplary wet coating system includes a coating chamber, an annealing chamber, an unloading chamber, and a mechanical arm. The coating chamber is configured for allowing a substrate being wet coated therein. The unloading chamber is configured for allowing the substrate being unloaded therein. The annealing chamber is interposed between and communicated with the coating chamber and the unloading chamber and is configured for allowing the substrate being annealed therein. The communicated coating chamber, annealing chamber, and unloading chamber are vacuumized. The mechanical arm is configured for holding the substrate and moving the substrate across the coating chamber, the annealing chamber, and the unloading chamber. | 02-10-2011 |
20110031108 | SPUTTERING DEPOSITION METHOD AND APPARATUS - A sputtering deposition method is utilized by a sputtering deposition apparatus including a first chamber, a second chamber, a first carrier, and a second carrier. Some first substrates are positioned in the first carriers in the first chamber for heating. The first carriers in the first chamber and the second carriers in the second chamber are exchanged. The first substrates in the second chamber are sputtered. The second carriers in the first chamber and the first carriers in the second chamber are exchanged. The first substrates in the first chamber are taken out. | 02-10-2011 |
20110051244 | ARTICLE HAVING METAL DIELECTRIC REFLECTIVE FILM - A article includes a substrate and a metal dielectric reflective film. The metal dielectric reflective film is formed on the substrate, the metal dielectric reflective film includes a dielectric multiple layer and a metal layer. The dielectric multiple layer includes a first layer, a second layer, a third layer, and a fourth layer arranged in the order written and stacked one on another. The first and third layers comprised of a low refractive index material, the second and fourth layers comprised of a high refractive index material. The metal layer is disposed on the fourth layer. | 03-03-2011 |
20110174607 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. A portion of the color layer corresponding to and located over the smooth region has a value for L* in a range from about 70.44 to about 72.44, a value for a* in a range from about −7.84 to about −6.84 and a value for b* in a range from about −8.57 to about −7.57 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174661 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and the color layer together. The color layer includes at least one metal layer. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 40.34 to about 42.34, a value of a* in a range from about 0.11 to about 1.11 and a value of b* in a range from about 2.24 to about 3.24 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174662 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. Portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 17.93 to about 19.93, a value of a* in a range from about 23.74 to about 24.74 and a value of b* in a range from about 2.20 to about 3.20 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174663 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and the color layer together. The color layer includes at least one metal layer. Portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 57.57 to about 59.57, a value of a* in a range from about 1.04 to about 2.04 and a value of b* in a range from about 6.64 to about 7.64 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174664 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and the color layer together. The color layer includes at least one metal layer. Portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 81.59 to about 83.59, a value of a* in a range from about −0.55 to about 0.45 and a value of b* in a range from about −0.60 to about 0.40 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174666 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region, and the color layer is located over the smooth region of the base. The color layer includes titanium, and has a value for L* in the range from 51.55 to 52.55, a value for a* in the range from 13.12 to 14.12 and a value for b* in the range from 6.27 to 7.27 according to the Commission Internationale del'Eclairage, (CIE, International Commission on Illumination) LAB system. The bonding layer is located between the substrate and the color layer, providing adhesion therebetween. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174667 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 32.51 to about 34.51, a value of a* in a range from about −8.74 to about −7.74 and a value of b* in a range from about −12.39 to about −11.39 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174668 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 50.77 to about 52.77, a value of a* in a range from about −0.93 to about 0.07 and a value of b* in a range from about −1.26 to about −0.26 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174669 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. Portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 59.12 to about 61.12, a value of a* in a range from about 0.17 to about 1.17 and a value of b* in a range from about 2.40 to about 3.40 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174670 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 81.43 to about 83.43, a value of a* in a range from about 0.30 to about 1.30 and a value of b* in a range from about 2.11 to about 3.11 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174671 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 36.54 to about 38.54, a value of a* in a range from about 0.04 to about 1.04 and a value of b* in a range from about 1.88 to about 2.88 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174672 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 49.07 to about 51.07, a value of a* in a range from about 0.19 to about 1.19 and a value of b* in a range from about 1.94 to about 2.94 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174673 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 81.76 to about 83.76, a value of a* in a range from about −0.63 to about 0.37 and a value of b* in a range from about −1.04 to about −0.04 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110174674 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 51.00 to about 53.00, a value of a* in a range from about −1.04 to about −0.04 and a value of b* in a range from about 1.88 to about 2.88 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110175500 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. A portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 75.26 to about 77.26, a value of a* in a range from about 0.42 to about 1.42 and a value of b* in a range from about 9.36 to about 10.36 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110177351 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes at least one metal layer. Portion of the color layer corresponding to and located over the smooth region has a value for L* in a range from about 18.14 to about 19.14, a value for a* in a range from about 13.39 to about 14.39 and a value for b* in a range from about −32.46 to about −31.46 according to the Commission Internationale del'Eclairage LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
20110177357 | COLORED DEVICE CASING AND SURFACE-TREATING METHOD FOR FABRICATING SAME - A colored device casing includes a base, a color layer and a bonding layer. The base has at least one smooth region. The bonding layer is positioned between the base and the color layer and bonds the base and color layer together. The color layer includes titanium. Portion of the color layer corresponding to and located over the smooth region has a value of L* in a range from about 39.68 to about 41.68, a value of a* in a range from about 4.80 to about 5.80 and a value of b* in a range from about 6.88 to about 7.88 according to the Commission Internationale del'Eclairage, (CIE, International Commission on Illumination) LAB system. A surface-treating method for fabricating the colored casing is also provided. | 07-21-2011 |
Patent application number | Description | Published |
20100052076 | METHOD OF FABRICATING HIGH-K POLY GATE DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 03-04-2010 |
20100096705 | IMPLANTATION METHOD FOR REDUCING THRESHOLD VOLTAGE FOR HIGH-K METAL GATE DEVICE - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer. | 04-22-2010 |
20100105185 | REDUCING POLY-DEPLETION THROUGH CO-IMPLANTING CARBON AND NITROGEN - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively. | 04-29-2010 |
20100156572 | CARRIER FOR TRANSMITTING HIGH FREQUENCY SIGNAL AND CARRIER LAYOUT METHOD THEREOF - A carrier for transmitting a high frequency signal and a carrier layout method thereof are provided. The carrier includes a substrate, conducting wires and reference planes both formed on the substrate. The carrier layout method includes defining impedance and thickness of the carrier according to the high frequency signal and defining layout parameters according to the impedance and the thickness. The layout parameters include a conducting layer formed on the conducting wires, a coplanar waveguide formed between the reference planes and the conducting wires, roughness portions formed on the conducting wires, recessed portions formed on the conducting wires, and the substrate being a high loss tangent substrate. The layout is performed according to the layout parameters defined thereabove, so as to increase loss of the high frequency signal in transmission. | 06-24-2010 |
20110117734 | Method of Fabricating High-K Poly Gate Device - The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer. | 05-19-2011 |
20110272766 | High-K Metal Gate Device - A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F. | 11-10-2011 |
Patent application number | Description | Published |
20120267767 | SEMICONDUCTOR OVERLAPPED PN STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 10-25-2012 |
20120280320 | High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions. | 11-08-2012 |
20130069153 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region. | 03-21-2013 |
20130181253 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth. | 07-18-2013 |
20130181319 | Trench Schottky Barrier Diode and Manufacturing Method Thereof - The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer. | 07-18-2013 |
20130313641 | DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed. | 11-28-2013 |
20130341719 | Hybrid High Voltage Device and Manufacturing Method Thereof - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 12-26-2013 |
20140021544 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 01-23-2014 |
20140151796 | HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 06-05-2014 |
20140151799 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 06-05-2014 |
20140315358 | MANUFACTURING METHOD OF JUNCTION FIELD EFFECT TRANSISTOR - The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step. | 10-23-2014 |
20150028417 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions. | 01-29-2015 |
20150123198 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region. | 05-07-2015 |