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Chiang-Lin Shih
Chiang-Lin Shih, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090111060 | EXPOSURE METHOD - An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result. | 04-30-2009 |
| 20100227069 | APPARATUS FOR REDUCING COST OF DEVELOPER AND THE METHOD THEREOF - An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced. | 09-09-2010 |
Chiang-Lin Shih, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100097596 | SCANNING EXPOSURE METHOD - A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate. | 04-22-2010 |
Chiang-Lin Shih, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080251933 | METAL INTERCONNECT STRUCTURE - A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction. | 10-16-2008 |
| 20090290134 | EXPOSURE METHOD - A method for exposure is provided to avoid a rise in temperature of a lens set. First, a light beam passes through a first light-receiving region of the lens set to expose a pattern on a substrate, and the first light-receiving region has a rise in temperature. Thereafter, the first light-receiving region is moved away. Afterwards, the light beam passes through a second light-receiving region of the lens set so that the first light-receiving region has a drop in temperature. | 11-26-2009 |
| 20100009294 | EXPOSURE METHOD - An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose. | 01-14-2010 |
Chiang-Lin Shih, Linkou Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090233448 | LITHOGRAPHY RESOLUTION IMPROVING METHOD - A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided. | 09-17-2009 |
Chiang-Lin Shih, Yunlin TW
| Patent application number | Description | Published |
|---|---|---|
| 20080286934 | METHOD OF FORMING A TRENCH CAPACITOR - A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench. | 11-20-2008 |