| Patent application number | Description | Published |
|---|
| 20080315919 | LOGIC STATE CATCHING CIRCUITS - A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element. | 12-25-2008 |
| 20090040801 | Content Addressable Memory - A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance. | 02-12-2009 |
| 20100023684 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A CONTENT ADDRESSABLE MEMORY - Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information. | 01-28-2010 |
| 20100148839 | Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains - Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation. | 06-17-2010 |
| 20100182823 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 07-22-2010 |
| 20110140752 | Adaptive Clock Generators, Systems, and Methods - Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s). | 06-16-2011 |
| 20110211386 | Low Leakage High Performance Static Random Access Memory Cell Using Dual-Technology Transistors - A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide. | 09-01-2011 |
| 20110227639 | Method and Apparatus for Suppressing Bitline Coupling Through Miller Capacitance to a Sense Amplifier Interstitial Node - A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs. | 09-22-2011 |
