| Patent application number | Description | Published |
|---|
| 20080266940 | Air Cell Thermal Isolation for a Memory Array Formed of a Programmable Resistive Material - A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element. | 10-30-2008 |
| 20090020746 | SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY - A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material. | 01-22-2009 |
| 20090148981 | METHOD FOR FORMING SELF-ALIGNED THERMAL ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY ARRAY - A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element. | 06-11-2009 |
| 20090236743 | Programmable Resistive RAM and Manufacturing Method - Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size. | 09-24-2009 |
| 20100015757 | BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD WITH A SINGULAR CONTACT STRUCTURE - A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process. | 01-21-2010 |
| 20100039846 | Method and Apparatus for Non-Volatile Multi-Bit Memory - A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer. | 02-18-2010 |
| 20100105165 | MULTILEVEL-CELL MEMORY STRUCTURES EMPLOYING MULTI-MEMORY LAYERS WITH TUNGSTEN OXIDES AND MANUFACTURING METHOD - The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member. | 04-29-2010 |
| 20100207095 | RESISTOR RANDOM ACCESS MEMORY CELL WITH L-SHAPED ELECTRODE - A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member. | 08-19-2010 |
| 20100221888 | Programmable Resistive RAM and Manufacturing Method - Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps. | 09-02-2010 |
| 20100301330 | Memory Devices Having an Embedded Resistance Memory with Metal-Oxygen Compound - Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element. | 12-02-2010 |
| 20110012084 | RESISTOR RANDOM ACCESS MEMORY CELL WITH REDUCED ACTIVE AREA AND REDUCED CONTACT AREAS - A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material. | 01-20-2011 |
