Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Chia-Wei Wu
Chia-Wei Wu, Jhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090061624 | METHOD OF FABRICATING INTEGRATED CIRCUIT WITH SMALL PITCH - A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls. | 03-05-2009 |
| 20110012192 | Vertical Channel Transistor Structure and Manufacturing Method Thereof - A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate. | 01-20-2011 |
Chia-Wei Wu, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080238454 | TESTER AND STRUCTURE OF PROBE THEREOF - A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test. | 10-02-2008 |
| 20090289649 | TESTER WITH LOW SIGNAL ATTENUATION - A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end. | 11-26-2009 |
Chia-Wei Wu, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080290397 | MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate. | 11-27-2008 |
| 20080299741 | Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation - An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide. | 12-04-2008 |
| 20090011574 | Method for surface modification of semiconductor layer and method of manufacturing semiconductor device - A method for surface modification of a semiconductor layer and a method of manufacturing a semiconductor device are provided. The method for surface modification of the silicon layer includes following steps. First, a semiconductor layer having several particles on its surface is provided. Next, these particles are removed through a clean process. In the clean process, the semiconductor layer is exposed to an organic matter remover, a first peroxide mixture solution and a second peroxide mixture solution sequentially. | 01-08-2009 |
| 20090091983 | NON-VOLATILE MEMORY STRUCTURE AND ARRAY THEREOF - A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively. | 04-09-2009 |