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Chia-Wei Chang
Chia-Wei Chang, Tainan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100277350 | GROUP KEYPADS IN COMPLIANCE WITH STANDARD KEYBOARD INSTALLATION - A group keypad structure in compliance with a standard keyboard installation includes group keypads corresponding to characters of a standard keyboard input method; for example, the structure includes ten group keypads installed from left to right on a base, and the ten group keypads include characters of “Q, A, Z”, “W, S, X”, “E, D, C”, “R, F, V”, “T, G, B”, “Y, H, N”, “U, J, M”, “I, K, ,”, “O, L, .” and “P, ;, /” respectively, and further includes ten numeric characters “ | 11-04-2010 |
Chia-Wei Chang, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100271612 | METHOD AND PELLICLE MOUNTING APPARATUS FOR REDUCING PELLICLE INDUCED DISTORTION - An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask. | 10-28-2010 |
Chia-Wei Chang, Taichung TW
| Patent application number | Description | Published |
|---|---|---|
| 20090051341 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor. | 02-26-2009 |
| 20090051342 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes an input circuit having a first FET, a second FET, and a first resistor, wherein a first node is connected to the first FET having a first threshold voltage, the first resistor is connected between a second node and the second FET having a second threshold voltage; a mirroring circuit for controlling two output currents respectively derived from the first and second nodes, and maintaining the two output currents to a specific current ratio; and an operation amplifier connected to the first node, the second node of the input circuit, and the mirroring circuit, for controlling two voltages respectively at the first and second nodes of the input circuit to a specific voltage ratio; wherein the first FET and the second FET are both operating in the subthreshold region, the first threshold voltage is larger than the second threshold voltage, and the two output currents are independent of temperature. | 02-26-2009 |
| 20100260952 | Furniture bow beam structure and manufacturing method thereof - A furniture bow beam structure and a manufacturing method thereof. By means of pressing, metal board materials are processed into different assembling members and connecting members. The assembling members and connecting members respectively have curvatures and configurations in conformity with different sections of the beam structure. Each assembling member has an opening that obliquely diverges to one side in width. The connecting member is connected to the opening and mated with the assembling member to form a hollow tubular support. Multiple supports are then connected with each other and rectified to form a complete beam structure with desired curvatures and shapes for connecting with other furniture components. | 10-14-2010 |
Chia-Wei Chang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100016585 | PHOSPHORUS-CONTAINING BISPHENOLS AND PREPARING METHOD THEREOF - The Phosphorus-containing bisphenols and preparing method thereof are disclosed. A method for producing the phosphorus-containing bisphenol of the general formula (1) includes reacting compounds respectively defined by a general formula (a), (b), (c) and an acid catalyst to yield compounds of phosphorus-containing bisphenol. | 01-21-2010 |
Chia-Wei Chang, Sinfong Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090115045 | Stacked package module and method for fabricating the same - The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package. | 05-07-2009 |
Chia-Wei Chang, Taichung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090040086 | DWA STRUCTURE AND METHOD THEREOF, DIGITAL-TO-ANALOG SIGNAL CONVERSION METHOD AND SIGNAL ROUTING METHOD - A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups. | 02-12-2009 |
| 20090110102 | SIGNAL ROUTING METHOD - A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits. | 04-30-2009 |
Chia-Wei Chang, Wufong Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090045482 | Shallow Trench Isolation with Improved Structure and Method of Forming - A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology. | 02-19-2009 |
Chia-Wei Chang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080224295 | Package structure and stacked package module using the same - A package structure with chip embedded therein is disclosed, which comprises a circuit board having a first surface, an opposite second surface and a through cavity penetrating the circuit board, wherein the first surface of the circuit board has a plurality of first conductive pads and a plurality of wire bonding pads disposed thereon, and the second surface of the circuit board has a plurality of second conductive pads disposed thereon; and a chip embedded in the through cavity of the circuit board, wherein the gap between the through cavity and the chip is filled with a filling material, the chip has an active surface with a plurality of electrode pads and an inactive surface, and the electrode pads electrically connect to the wire bonding pads of the circuit board by a plurality of metal lines. The present invention further provides a package module using the aforementioned package structure. | 09-18-2008 |
| 20080230892 | Chip package module - A chip package module is disclosed, which comprises a core plate and two rigid plates individually having a circuit layer. The core plate is sandwiched in between the two rigid plates to form a composite circuit board. Furthermore, the two rigid plates individually have a cavity to expose the surface of the core plate. In addition, the cavities individually have at least one chip disposed therein, and each chip electrically connects to the composite circuit board. The present invention reduces the height of the package module and makes the package module lighter and smaller. | 09-25-2008 |
Chia-Wei Chang, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110119761 | Mitigating Low-Rate Denial-of-Service Attacks in Packet-Switched Networks - A method includes determining, at a network routing device, an average packet drop rate for a plurality of aggregations of packet flows. The method also determines a threshold packet drop rate based on the average packet drop rate, a current packet drop rate for a select aggregation of the plurality of aggregations, and whether at least one packet flow of the select aggregation is potentially subject to a denial-of-service attack based on a comparison of the current packet drop rate to the threshold packet drop rate. | 05-19-2011 |
