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| 20100136245 | METHOD FOR MANUFACTURE AND STRUCTURE OF MULTIPLE ELECTROCHEMISTRIES AND ENERGY GATHERING COMPONENTS WITHIN A UNIFIED STRUCTURE - The present invention provides a method to design, manufacture and structure a multi-component energy device having a unified structure, wherein the individual components are chosen from the list consisting of electrochemical cells, photovoltaic cells, fuel-cells, capacitors, ultracapacitors, thermoelectric, piezoelectric, microelectromechanical turbines and energy scavengers. Said components are organized into a structure to achieve an energy density, power density, voltage range, current range and lifetime range that the single components could not achieve individually, i.e. to say the individual components complement each other. The individual components form a hybrid structure, wherein the elements are in electrical, chemical and thermal conduction with each other. The electrochemical cells present multiple chemistries to accommodate a wider range of voltage and current compared to individual ones; energy-scavenging elements are utilized to collect energy and replenish it to other components within the unified structure. | 06-03-2010 |
| 20100138072 | CONTROL OF CELLS, MODULES AND A PACK COMPRISED OF HYBRIDIZED ELECTROCHEMISTRIES - A power management apparatus for a hybridized energy device includes a hybridized energy device including a plurality of units. The units include electrical energy storage and/or gathering cells, in series or in parallel to form a module. A plurality of the modules in series or in parallel form a pack. The power management apparatus also includes a central management apparatus (CMA) interconnecting a plurality of module management apparatus (MMAs) by means of either wired or wireless connections and a plurality of MMAs. Each MMA interconnects with a plurality of unit management apparatuses by means of either wireless or wired communication circuits. The power management apparatus further includes a plurality of units management apparatuses (UMAs), each wired, connected with, or deposited on a unit. Furthermore, the power management apparatus includes a rechargeable battery power source for a CMA, a plurality of MMAs, and a plurality of UMAs. | 06-03-2010 |
| 20120041698 | METHOD AND SYSTEM FOR OPERATING A BATTERY IN A SELECTED APPLICATION - A method of the present invention using a prediction process including a battery equivalent circuit model used to predict a voltage and a state of charge of a battery. The equivalent circuit battery model includes different equivalent circuit models consisting of at least an ideal DC power source, internal resistance, and an arbitrary number of representative parallel resistors and capacitors. These parameters are obtained a priori by fitting the equivalent circuit model to battery testing data. The present invention further uses a correction process includes determining a corrected predicted state of charge of the battery; and storing the corrected state of charge of the battery in a storage medium. In the present invention, an expectation of the predicted voltage of the battery and an expectation of the predicted state of charge of the battery are obtained by an unscented transform with sigma points selected by a Gaussian process optimization. | 02-16-2012 |
| 20120046776 | COMPUTER AIDED SOLID STATE BATTERY DESIGN METHOD AND MANUFACTURE OF SAME USING SELECTED COMBINATIONS OF CHARACTERISTICS - A method of designing and manufacturing a solid-state electrochemical battery cell for a battery device. The method includes building a database of a plurality of first characteristics of a solid-state cells for a battery device and determining at least a third characteristic of the solid-state cell for a given application. The method also includes selecting at least one material of the solid-state electrochemical battery cell, the selected material being from the plurality of first characteristics and forming a plurality of factorial combinations of each component using the selected plurality of first characteristics to derive a respective plurality of solid-state electrochemical battery cells. The method performs a design optimization process for the third characteristic. A step of identifying an optimal design of the second characteristics with the selected first characteristics for each solid-state electrochemical battery cell from the plurality of solid-state cells is included. | 02-23-2012 |
| 20120058377 | ELECTRIC VEHICLE PROPULSION SYSTEM AND METHOD UTILIZING SOLID-STATE RECHARGEABLE ELECTROCHEMICAL CELLS - A vehicle propulsion system comprising a plurality of solid state rechargeable battery cells configured to power a drivetrain. In accordance with once aspect of the invention, a transportation system that is powered at least in part by electricity stored in the form of rechargeable electrochemical cells. According to an embodiment of the present invention, these cells are combined in series and in parallel to form a pack that is regulated by charge and discharge control circuits that are programmed with algorithms to monitor state of charge, battery lifetime, and battery health. | 03-08-2012 |
| 20120058380 | MONOLITHICALLY INTEGRATED THIN-FILM SOLID STATE LITHIUM BATTERY DEVICE HAVING MULTIPLE LAYERS OF LITHIUM ELECTROCHEMICAL CELLS - A monolithically integrated thin-film solid-state lithium battery device to supply energy to a mobile communication device. The battery device comprises multiple layers ranging from greater than 100 layers to less than 20,000 layers of lithium electrochemical cells. The lithium electrochemical cells are connected in parallel or in series to conform to a spatial volume. The device is substantially free from a substrate member. The overlying multiple layers are free from any intermediary substrate member. The multiple layers are configured to form a plurality of electrochemical cells configured in a parallel arrangement or a serial arrangement using either a self terminated or post terminated connector configuration. | 03-08-2012 |
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| 20090213656 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 08-27-2009 |
| 20090276737 | TOOL FOR CHARGE TRAPPING MEMORY USING SIMULATED PROGRAMMING OPERATIONS - A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants. | 11-05-2009 |
| 20100120210 | FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS - A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions. | 05-13-2010 |
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| 20080295062 | Method of verifying a layout pattern - A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns. | 11-27-2008 |
| 20090300576 | METHOD FOR AMENDING LAYOUT PATTERNS - A method for amending layout patterns is disclosed. First, a layout pattern after an optical proximity correction is provided, which is called an amended pattern. Later, a positive sizing procedure and a negative sizing procedure are respectively performed on the amended pattern to respectively obtain a positive sizing pattern and a negative sizing pattern. Then, the positive sizing pattern and the negative sizing pattern are respectively verified to know whether they are useable. Afterwards, the useable positive sizing pattern and the negative sizing pattern are output for the manufacture of a reticle when they are verified to be useable. | 12-03-2009 |
| 20100131914 | METHOD TO DETERMINE PROCESS WINDOW - A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output. | 05-27-2010 |
