Patent application number | Description | Published |
20100004734 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 01-07-2010 |
20120232643 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 09-13-2012 |
20120232644 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 09-13-2012 |
20140035192 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 02-06-2014 |
20140039600 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 02-06-2014 |
20140236285 | STENT FABRICATION VIA TUBULAR CASTING PROCESSES - Tubular casting processes, such as dip-coating, may be used to form substrates from polymeric solutions which may be used to fabricate implantable devices such as stents. The polymeric substrates may have multiple layers which retain the inherent properties of their starting materials and which are sufficiently ductile to prevent brittle fracture. Parameters such as the number of times the mandrel is immersed, the duration of time of each immersion within the solution, as well as the delay time between each immersion or the drying or curing time between dips and withdrawal rates of the mandrel from the solution may each be controlled to result in the desired mechanical characteristics. Additional post-processing may also be utilized to further increase strength of the substrate or to alter its shape. | 08-21-2014 |
Patent application number | Description | Published |
20080217662 | Space-efficient package for laterally conducting device - Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package. | 09-11-2008 |
20090250796 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 10-08-2009 |
20110003439 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY ELECTROPLATING - Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package. | 01-06-2011 |
20110024886 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 02-03-2011 |
20110291254 | SEMICONDUCTOR DEVICE PACKAGE FEATURING ENCAPSULATED LEADFRAME WITH PROJECTING BUMPS OR BALLS - Embodiments of the present invention relate to semiconductor device packages featuring encapsulated leadframes in electrical communication with at least one die through electrically conducting bumps or balls and electrically conducting ribbons. Embodiments of the present invention may permit multiple die and/or multiple passive devices to occupy space in the package previously consumed by the diepad. The result is a flexible packaging process allowing the combination of die and technologies required for complete sub-systems in a conventional small JEDEC specified footprint. | 12-01-2011 |
20120056261 | BI-DIRECTIONAL, REVERSE BLOCKING BATTERY SWITCH - Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package. | 03-08-2012 |
20120181676 | POWER SEMICONDUCTOR DEVICE PACKAGING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20120181677 | SEMICONDUCTOR DEVICE PACKAGE WITH TWO COMPONENT LEAD FRAME - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features. | 07-19-2012 |
20130009296 | SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING - Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body. | 01-10-2013 |
20130009297 | SEMICONDUCTOR DEVICE PACKAGE HAVING CONFIGURABLE LEAD FRAME FINGERS - Embodiments of the present invention relate to the use of configurable lead frame fingers in a semiconductor device package. More specifically, the lead frame of a device package can include a plurality of fingers used to support and provide electrical contact to the die. The die can include a plurality of contacts that comprise a series of parallel columns located a certain distance from one another, and the fingers of the lead frame can be configured to align with the contacts. The lead frame can have multiple terminals, each with one or more fingers and pins. As such, each lead frame configuration may be utilized with different configurations of die. | 01-10-2013 |
20130017652 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE WITH A HEATSINK - Embodiments of the present invention relate to forming semiconductor device package with a heat sink. In one embodiment, a subassembly comprising a die attached to a lead frame is formed, a heat sink is provided in a molding cavity, and the subassembly is coupled to the heat sink while the heat sink is in the molding cavity. In certain embodiments, a second component of the lead frame can be substituted for the heat sink. Such techniques can simplify the manufacturing process for semiconductor packages having a heat sink or lead frame with a second component. | 01-17-2013 |
Patent application number | Description | Published |
20090204026 | Safety Blood Collection Assembly With Indicator - A blood collection assembly includes a housing and a cannula extending distally from the housing including a patient end, and a cannula shield removably engaged with a portion of the housing. The cannula shield is capable of shielding at least the patient end of the cannula, and includes a safety shield engagement. The assembly includes a pivoting safety shield engaged with a portion of the housing, which is transitionable from a retracted position in which the patient end of the cannula is exposed, to an extended position in which the patient end of the cannula is shielded by at least a portion of the safety shield. The safety shield includes at least one locking tab releasably engageable with the safety shield engagement, wherein the locking tab is fixedly engageable with a portion of the housing in the extended position. | 08-13-2009 |
20110166474 | Safety Blood Collection Assembly with Indicator - A needle assembly is disclosed. The needle assembly includes a housing having a flash chamber, and having a distal end and a proximal end engageable with a specimen collection container. The assembly includes a cannula having a patient end, a non-patient end, and a sidewall extending therebetween defining a cannula interior. The patient end of the cannula projects at least partially from the distal end of the housing, and the cannula interior is in fluid communication with the flash chamber. The assembly further includes a shield restrainably engaged with a portion of the housing and axially transitionable over the patient cannula from a retracted position in which the patient end is exposed, to an extended position in which the patient end is shielded by at least a portion of the shield, wherein at least a portion of the flash chamber is visible in the retracted position. | 07-07-2011 |
20110166475 | Safety Blood Collection Assembly with Indicator - A needle assembly is disclosed. The needle assembly includes a housing having a flash chamber, and having a distal end and a proximal end engageable with a specimen collection container. The assembly includes a cannula having a patient end, a non-patient end, and a sidewall extending therebetween defining a cannula interior. The patient end of the cannula projects at least partially from the distal end of the housing, and the cannula interior is in fluid communication with the flash chamber. The assembly further includes a shield restrainably engaged with a portion of the housing and axially transitionable over the patient cannula from a retracted position in which the patient end is exposed, to an extended position in which the patient end is shielded by at least a portion of the shield, wherein at least a portion of the flash chamber is visible in the retracted position. | 07-07-2011 |
20110166476 | Safety Blood Collection Assembly with Indicator - A needle assembly is disclosed. The needle assembly includes a housing having a flash chamber, and having a distal end and a proximal end engageable with a specimen collection container. The assembly includes a cannula having a patient end, a non-patient end, and a sidewall extending therebetween defining a cannula interior. The patient end of the cannula projects at least partially from the distal end of the housing, and the cannula interior is in fluid communication with the flash chamber. The assembly further includes a shield restrainably engaged with a portion of the housing and axially transitionable over the patient cannula from a retracted position in which the patient end is exposed, to an extended position in which the patient end is shielded by at least a portion of the shield, wherein at least a portion of the flash chamber is visible in the retracted position. | 07-07-2011 |
20140358037 | Safety Blood Collection Assembly with Indicator - A blood collection assembly includes a housing and a cannula extending distally from the housing including a patient end, and a cannula shield removably engaged with a portion of the housing. The cannula shield is capable of shielding at least the patient end of the cannula, and includes a safety shield engagement. The assembly includes a pivoting safety shield engaged with a portion of the housing, which is transitionable from a retracted position in which the patient end of the cannula is exposed, to an extended position in which the patient end of the cannula is shielded by at least a portion of the safety shield. The safety shield includes at least one locking tab releasably engageable with the safety shield engagement, wherein the locking tab is fixedly engageable with a portion of the housing in the extended position. | 12-04-2014 |
Patent application number | Description | Published |
20080265414 | Electrically Conductive Composite - The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm | 10-30-2008 |
20090004402 | Radiation Crosslinker - There is provided a class of crosslinking compound, said compound comprising (i) one or more fluorinated aromatic group; and (ii) one or more ionisable group, wherein the crosslinking compound is soluble in at least one polar solvent. Methods of preparing the crosslinking compounds are also disclosed. There is further provided devices obtainable from the methods of preparing the crosslinking compounds. | 01-01-2009 |
20110052813 | FUNCTIONALISED GRAPHENE OXIDE - A functionalised graphene oxide and a method of making a functionalised graphene oxide comprising: (i) oxidizing graphite to form graphite oxide wherein the graphene sheets which make up the graphite independently of each other have a basal plane fraction of carbon atoms in the sp | 03-03-2011 |
20110089406 | MULTILAYER HETEROSTRUCTURES FOR APPLICATION IN OLEDS AND PHOTOVOLTAIC DEVICES - This invention relates to a supported polymer heterostructure and methods of manufacture. The heterostructure is suitable for use in a range of applications which require semiconductor devices, including photovoltaic devices and light-emitting diodes. | 04-21-2011 |
20120244294 | CROSS-LINKING MOIETY - A cross-linking moiety having a general formula I: N | 09-27-2012 |
20150287923 | MULTILAYER HETEROSTRUCTURES FOR APPLICATION IN OLEDS AND PHOTOVOLTAIC DEVICES - This invention relates to a supported polymer heterostructure and methods of manufacture. The heterostructure is suitable for use in a range of applications which require semiconductor devices, including photovoltaic devices and light-emitting diodes. | 10-08-2015 |
Patent application number | Description | Published |
20130288625 | Radio Receiver with Adaptive Tuner - A mobile radio receiver for a vehicle. The mobile radio receiver includes a tuner front-end section, a location data port, a sensor port, and a data processing unit. The location data port is used for receiving tuner location data. The sensor port is used for receiving one or more sensor signals. The data processing unit is operably connected with the tuner front-end section, with the location data port, and with the sensor port. The data processing unit further comprises predetermined tuner location data and predetermined relationship data sets for determining a set of tuner front-end section parameters based on the sensor signals. The mobile radio receiver provides an operational mode, a checking mode, a tuner parameter adjustment mode, and a tuner parameter application mode. | 10-31-2013 |
20140194079 | INCREASING EFFICIENCY OF A RADIO RECEIVER WITH AN ADAPTIVE TUNER - A mobile radio receiver for a vehicle includes a tuner front-end section, a location data port for receiving tuner location data, a sensor port for receiving sensor signal measurement data from at least one vehicle sensor, a tuner front-end section parameter server port for sending the tuner location data, the sensor signal measurement data for receiving a set of tuner front-end section parameter data, and a data processing unit. The data processing unit is operably connected to the tuner front-end section, the location data port, the sensor port, and the tuner front-end section parameter server port. The mobile radio receiver provides an operational mode, a checking mode, a tuner parameter retrieval mode, and a tuner parameter application mode. | 07-10-2014 |
20150061646 | ADAPTABLE VOLTAGE LEVEL DETECTION WITH RESISTIVE LADDER - A switch actuation detection unit has a switch actuation voltage reception terminal and a logic circuit. The logic circuit includes a first port, a second port, a zener diode, and a signal port. The switch actuation voltage reception terminal receives a switch actuation voltage. The first port is connected to the switch actuation voltage reception terminal. A first terminal of the zener diode is connected to the switch actuation voltage reception terminal while a second terminal of the zener diode is connected to the second port. The signal port provides a plurality of pre-determined switch state signals. | 03-05-2015 |
20150263771 | EFFICIENCY AND OPTIMIZATION OF RF TUNER RECEPTION THROUGH INTER-CAR CORRELATION - A mobile radio receiver for a vehicle includes a tuner front-end section, an inter-vehicle communication port, and a data processing unit. The data processing unit is operably connected with the tuner front-end section and with the inter-vehicle communication port. The data processing unit has at least two pre-determined relationship data sets. In use, the inter-vehicle communication port receives a tuner front-end section parameter data pointer. The pre-determined relationship data sets are used to determine a set of tuner front-end section parameters based on the tuner front-end section parameter data pointer. The mobile radio receiver provides an operational mode, a parameter reception mode, a tuner parameter adjustment mode, and a tuner parameter application mode. | 09-17-2015 |
Patent application number | Description | Published |
20090128204 | Time delay apparatus - A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by. phase shifting the digital signal according to the phase control signal. | 05-21-2009 |
20100315145 | APPARATUS FOR GENERATING A PLURALITY OF SIGNALS - An apparatus for generating a plurality of signals is provided. The apparatus provided includes a first signal generation unit, including an input receiving a reference signal, and a plurality of outputs providing a first plurality of output signals being generated based on the reference signal, wherein any two of the output signals have a different phase. The apparatus provided further includes a second signal generation unit, including at least two inputs receiving at least two signals selected from the first plurality of output signals generated by the first signal generation unit, and a plurality of outputs providing a second plurality of output signals generated by interpolating the respective phases of the received at least two signals selected from the first plurality of output signals. The apparatus provided further includes a selection unit, including a first plurality of inputs receiving the first plurality of output signals generated by the first signal generation unit, a second plurality of inputs receiving the second plurality of output signals generated by the second signal generation unit, and a plurality of outputs providing the plurality of signals wherein each of the signals is selected from the first plurality of output signals generated by the first signal generation unit and the second plurality of output signals generated by the second signal generation unit, wherein any two signals of the plurality of signals have a different phase. | 12-16-2010 |
20110102079 | High efficiency linear amplifier - A high efficiency linear amplifier is disclosed. The amplifier comprises an input module having an input coupled to receive an input signal, a first output configured to provide a first signal component, and a second output configured to provide a second signal component. The amplifier also comprises a switching module having a switch input coupled to receive a switch signal, a first input coupled to the first output of the input module, a second input coupled to the second output of the input module, and at least a first output configured to provide a first composite signal. The amplifier further comprises an amplifier module having at least a first input coupled to the first output of the switching module and at least a first output, wherein the first and second signal components comprise constant envelope phase varying signals having different phase relationships and which correspond to the input signal, and wherein the first composite signal comprises temporally sequenced portions of the first and second signal components. | 05-05-2011 |
Patent application number | Description | Published |
20080211113 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 09-04-2008 |
20090014858 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 01-15-2009 |
20090102002 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor packages, packaged semiconductor devices, methods of manufacturing semiconductor packages, methods of packaging semiconductor devices, and associated systems are disclosed. A semiconductor package in accordance with a particular embodiment includes a die having a first side carrying a first bond site electrically connected to a sensor and/or a transmitter configured to receive and/or transmit radiation signals. The semiconductor package also includes encapsulant material at least partially encapsulating a portion of the die. The semiconductor package includes a conductive path from the first bond site to a second bond site, positioned on a back surface of the encapsulant, which can include through-encapsulant interconnects. A cover can be positioned adjacent to the die and be generally transparent to a target wavelength. | 04-23-2009 |
20100072603 | SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES WITH EDGE CONTACTS AND SACRIFICIAL SUBSTRATES AND OTHER INTERMEDIATE STRUCTURES USED OR FORMED IN FABRICATING THE ASSEMBLIES OR PACKAGES - A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device. | 03-25-2010 |
20100146780 | METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS - A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly. | 06-17-2010 |
20110018143 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 01-27-2011 |
20120064697 | METHOD FOR PACKAGING CIRCUITS - A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly. | 03-15-2012 |
20120119263 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 05-17-2012 |
20140015130 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing. | 01-16-2014 |
20140124960 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 05-08-2014 |
20140141544 | PACKAGED MICROELECTRONIC COMPONENTS - A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package. | 05-22-2014 |
20140242751 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 08-28-2014 |
20150091166 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing. | 04-02-2015 |
20150325554 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 11-12-2015 |