| Patent application number | Description | Published |
|---|
| 20080217675 | Novel profile of flash memory cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 09-11-2008 |
| 20080227276 | Silicon Substrate With Reduced Surface Roughness - The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer | 09-18-2008 |
| 20080237761 | SYSTEM AND METHOD FOR ENHANCING LIGHT SENSITIVITY FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A system and method for enhancing light sensitivity of a back-side illumination image sensor are described. An integrated circuit includes a substrate and an image sensor device comprising at least one transistor formed over a first surface of the substrate and a photosensitive region. A color filter is disposed over a second surface of the substrate opposite the first surface thereof. A micro-lens structure is disposed between the second surface of the substrate and the color filter. | 10-02-2008 |
| 20080248620 | Gated semiconductor device and method of fabricating same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 10-09-2008 |
| 20090020842 | EMBEDDED BONDING PAD FOR BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provide a microelectronic device. The microelectronic device includes a sensing element formed in the semiconductor substrate; a trench isolation feature formed in the semiconductor substrate; a bonding pad formed at least partially in the trench isolation feature; and interconnect features formed over the sensing element and the trench isolation feature, being coupled to the sensing element and the bonding pad, and isolated from each other by interlayer dielectric. | 01-22-2009 |
| 20090026432 | METHOD AND STRUCTURE FOR UNIFORM CONTACT AREA BETWEEN HEATER AND PHASE CHANGE MATERIAL IN PCRAM DEVICE - A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process. | 01-29-2009 |
| 20090029547 | NOVEL LADDER POLY ETCHING BACK PROCESS FOR WORD LINE POLY PLANARIZATION - A method is disclosed for etching a polysilicon material in a manner that prevents formation of an abnormal polysilicon profile. The method includes providing a substrate with a word line and depositing a polysilicon layer over said substrate and word line. An organic bottom antireflective coating (BARC) layer is then deposited over said polysilicon layer. A ladder etch is performed to remove the BARC layer and a portion of the polysilicon layer. The ladder etch consists of a series of etch cycles, with each cycle including a breakthrough etch and a soft landing etch. The breakthrough and soft landing etches are performed using different etchant gases, and at different source and bias powers, pressures, gas flow rates, and periods of time. The ladder etch results in a smooth polysilicon surface without abrupt steps. | 01-29-2009 |
| 20090209050 | In-Situ Formed Capping Layer in MTJ Devices - A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers. | 08-20-2009 |
| 20100062611 | Method and Apparatus for Thinning a Substrate - Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH. | 03-11-2010 |
| 20100193891 | In-Situ Formed Capping Layer in MTJ Devices - A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers. | 08-05-2010 |
| 20100213431 | Treated Chalcogenide Layer for Semiconductor Devices - A phase change memory and a method of manufacture are provided. The phase change memory includes a layer of phase change material treated to increase the hydrophobic nature of the phase change material. The hydrophobic nature of the phase change material improves adhesion between the phase change material and an overlying mask layer. The phase change material may be treated, for example, with a plasma comprising N | 08-26-2010 |
| 20100244287 | METHOD OF MEASUREMENT IN SEMICONDUCTOR FABRICATION - Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process. | 09-30-2010 |
| 20100248414 | METHOD OF WAFER BONDING - Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate. | 09-30-2010 |
| 20100248446 | METHOD AND APPARATUS OF HOLDING A DEVICE - Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. | 09-30-2010 |
| 20110006355 | Novel Structure for Flash Memory Cells - A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic. | 01-13-2011 |
| 20110165746 | Novel Profile of Flash Memory Cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 07-07-2011 |
