| Patent application number | Description | Published |
|---|
| 20110193175 | LOWER PARASITIC CAPACITANCE FINFET - An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer. | 08-11-2011 |
| 20110207279 | INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 08-25-2011 |
| 20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 09-01-2011 |
| 20110227162 | METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD - A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET. | 09-22-2011 |
| 20110248348 | Hybrid Gate Process For Fabricating Finfet Device - Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches. | 10-13-2011 |
| 20120015493 | INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 01-19-2012 |
| Patent application number | Description | Published |
|---|
| 20090047006 | FAN SYSTEM AND MOTOR CONTROL DEVICE - A fan system includes a control device and a fan device. The control device has a first node, a rotation speed signal generation circuit and a rotation speed reading circuit. The fan device has a second node, a signal transforming circuit, a motor driving circuit, a motor and a fan. The first node is electrically connected with the second node to set up a transmission route between the control device and the fan device. The rotation speed control signal and the motor rotation speed signal are transmitted via the two-way transmission route, and the control device controls the fan device via a wired or wireless transmission route. A motor control device is also disclosed. | 02-19-2009 |
| 20100134054 | FAN AND MOTOR CONTROL DEVICE - A fan includes a motor control device which is electrically connected with a motor and an alternating current power source. The motor control device includes a converting circuit, a power factor correction circuit and a motor controlling circuit. The voltage of the alternating current power source is converted to be direct current voltage by the converting circuit and the power factor correction circuit, and then the direct current voltage is outputted to the motor control circuit. The motor controlling circuit generates a driving signal in accordance with the direct current voltage for driving the motor to operate. | 06-03-2010 |
| 20100149699 | MOTOR DETECTING AND PROTECTING APPARATUS AND ITS METHOD - A motor detecting and protecting apparatus electrically connected with a motor. The motor detecting and protecting apparatus includes a detecting unit, an error determining unit, a controlling unit and a driving unit. The detecting unit detects a state of the motor and outputs at least one first detecting signal and at least one second detecting signal to the error determining unit. The error determining unit has a first predetermined value, wherein the error determining unit outputs a warning signal to the controlling unit while a variation value between the first detecting signal and the second detecting signal exceeds the first predetermined value. And the controlling unit will control the motor to stop operating by the driving unit in accordance with the warning signal. And a motor detecting and protecting method is also disclosed. | 06-17-2010 |
