Patent application number | Description | Published |
20080204561 | METHOD FOR DETECTING DIGITAL VIDEO INTERFACE OFF-LINE MODE AND ASSOCIATED RECEIVER - A TMDS receiver includes a plurality of data channels, a clock channel, and an off-line mode detector. Each data channel receives a video signal and the clock channel receives a clock signal. Each data channel comprises a channel decoder for decoding the signals received by the corresponding receiving channel. The off-line mode detector detects an off-line mode detector, and then turns on a plurality of first data channels for a first predetermined period to determine an operation mode of video signal transmitted on said first data channels if the activity of the clock signal is valid. The off-line mode detector also activates a plurality of second data channels among the plurality of data channels according to the operation mode if the operation mode is determined as valid. | 08-28-2008 |
20090289247 | Organic-semiconductor-based infrared receiving device - An organic-semiconductor-based infrared receiving device comprises an electrode layer having a positive layer and a negative layer to form an electric field, and a transport layer located between the positive and negative layers and having a first and a second predetermined material combined in a predetermined ratio. The energy of infrared light from a light source is received at an interface between the first and second materials. The thickness of the transport layer can be increased to enhance the light absorbance in the infrared light range to form electron-hole pairs, which are then parted to form a plurality of electrons and holes driven by the electric field to move to the negative layer and the positive layer, respectively, so that a predetermined photocurrent is generated. | 11-26-2009 |
20100133434 | Organic semiconductor infrared distance sensing apparatus and organic infrared emitting apparatus thereof - An organic semiconductor infrared distance sensing apparatus and an organic infrared emitting apparatus thereof are disclosed. The organic semiconductor infrared distance sensing apparatus comprises an organic infrared emitting apparatus and an organic infrared receiving apparatus. The organic infrared emitting apparatus has a positive electrode layer and a negative electrode layer to form an electric field, and organic light emitting molecules are sandwiched between the two layers and correspond to the positive electrode layer and the negative electrode layer. Under a positive bias, a plurality of electrons and holes are respectively injected from electrodes and recombine with each other to emit photons. An infrared organic conversion layer absorbs and transfers the energy to infrared emitting molecules to emit infrared light. The organic infrared receiving apparatus receives the infrared light reflected by an obstacle to generate photocurrent which varies with distance, thereby sensing the distance between the obstacle and the apparatus. | 06-03-2010 |
Patent application number | Description | Published |
20090154040 | MEMORY CARD WITH ELECTROSTATIC DISCHARGE PROTECTION AND MANUFACTURING METHOD THEREOF - A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board. | 06-18-2009 |
20090189295 | STACK CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire. | 07-30-2009 |
20090253230 | METHOD FOR MANUFACTURING STACK CHIP PACKAGE STRUCTURE - A method for manufacturing a stack chip package structure is disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire. | 10-08-2009 |
20120038839 | MICRO PROJECTOR MODULE - A micro projector module according to the present invention is provided. The micro projector module includes a substrate, a controller chip, a LCOS chip, a glass and a liquid crystal layer. The controller chip is positioned on the upper surface of the substrate and electrically connected to the substrate. The LCOS chip is positioned on the controller chip and electrically connected to the substrate. The glass is positioned on the LCOS chip and the liquid crystal layer is disposed between the LCOS chip and glass. | 02-16-2012 |
Patent application number | Description | Published |
20120280297 | DRAM WITH DOPANT STOP LAYER AND METHOD OF FABRICATING THE SAME - A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br. | 11-08-2012 |
20130234280 | SHALLOW TRENCH ISOLATION IN DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time. | 09-12-2013 |
20140264774 | WAFER AND FILM COATING METHOD OF USING THE SAME - The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region. | 09-18-2014 |
20140312401 | MEMORY CELL HAVING A RECESSED GATE AND MANUFACTURING METHOD THEREOF - A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate. | 10-23-2014 |