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Chia-Ling

Chia-Ling Chen, Boston, MA US

Patent application numberDescriptionPublished
20100038794THREE DIMENSIONAL NANOSCALE CIRCUIT INTERCONNECT AND METHOD OF ASSEMBLY BY DIELECTROPHORESIS - An assembly of nanoelements forms a three-dimensional nanoscale circuit interconnect for use in microelectronic devices. A process for producing the circuit interconnect includes using dielectrophoresis by applying an electrical field across a gap between vertically displaced non-coplanar microelectrodes in the presence of a liquid suspension of nanoelements such as nanoparticles or single-walled carbon nanotubes to form a nanoelement bridge connecting the microelectrodes. The assembly process can be carried out at room temperature, is compatible with conventional semiconductor fabrication, and has a high yield. The current-voltage curves obtained from the nanoelement bridge demonstrate that the assembly is functional with a resistance of −40 ohms for gold nanoparticles. The method is suitable for making high density three-dimensional circuit interconnects, vertically integrated nanosensors, and for in-line testing of manufactured conductive nanoelements.02-18-2010

Chia-Ling Ho, Ruifang Town TW

Patent application numberDescriptionPublished
20100241414DEBUGGING SIMULATION WITH PARTIAL DESIGN REPLAY - A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models. Each executed replay engine simulates behavior of each output signal of a corresponding low-level module in response to the data recorded during the initial simulation representing the behavior of that output signal.09-23-2010

Chia-Ling Hsu, Hsinchu City TW

Patent application numberDescriptionPublished
20110157884OPTOELECTRONIC DEVICE - A light-emitting device includes an insulating carrier; a light-emitting array formed on the insulating carrier including a first light-emitting circuit having a first light-emitting unit, wherein the first light-emitting circuit is a one-way circuit, a second light-emitting circuit having a second light-emitting unit, wherein the second light-emitting circuit is a one-way circuit, a first conductive layer, a second conductive layer, and a third conductive layer, wherein the first light-emitting circuit is formed between the first conductive layer and the second conductive layer and connects with them electrically, the second light-emitting circuit is formed between the second conductive layer and the third conductive layer and connects with them electrically, wherein an area of the second conductive layer is greater or equal to 1.9×1006-30-2011

Chia-Ling Ko, Kaohsiung TW

Patent application numberDescriptionPublished
20100313791CALCIUM PHOSPHATE BONE CEMENT, PRECURSOR THEREOF AND FABRICATION METHOD THEREOF - The invention provides a calcium phosphate bone cement, a precursor and a fabrication method thereof. The fabrication method comprises: (a) dissolving a calcium phosphate with a low Ca/P atomic ratio in an acid solution, wherein the Ca/P atomic ratio is less than 1.33; (b) adding a calcium phosphate compound into the acid solution to obtain a reaction solution; (c) allowing the reaction solution to stand to grow nanocrystallites on surfaces of the calcium phosphate with low Ca/P atomic ratio; (d) filtering and drying the solution of step (c) to obtain a calcium phosphate powder with low Ca/P atomic ratio having nanocrystallites on the surface; and (e) mixing the powder of step (d) and a calcium phosphate powder with a high Ca/P atomic ratio.12-16-2010

Chia-Ling Li, New Taipei City TW

Patent application numberDescriptionPublished
20110297975LIGHT-EMITTING UNIT ARRAY - A light-emitting unit array includes a plurality of light-emitting units arranged and integrated monolithically in an array, and each of the light-emitting units includes a first doped type layer, a second doped type layer, a light-emission layer, and a photonic crystal structure. The light emission layer is disposed between the first doped type layer and the second doped type layer, wherein the second doped type layer has a surface facing away from the light emission layer. The photonic crystal structure is disposed on the surface of the second doped type layer.12-08-2011
20110299044PROJECTION APPARATUS - A projection apparatus is provided. The projection apparatus includes a light-emitting unit array, an optical sensor, and a control unit. The light-emitting unit array is for emitting an image beam. The optical sensor is for detecting electromagnetic waves so as to generate a signal. The control unit is electrically coupled to the light-emitting unit array and the optical sensor for controlling emission of the light-emitting unit array according to the signal from the optical sensor.12-08-2011

Chia-Ling Liu, Taipei TW

Patent application numberDescriptionPublished
20100134375PLANAR ANTENNA - A planar antenna includes: a substrate unit; a feeding line provided on the substrate unit and having first and second ends, a feeding point disposed between the first and second ends, and first and second feeding segments extending from the feeding point in opposite directions to the first and second ends, respectively, the lengths of the first and second feeding segments having a length difference that is approximately λ/2, where λ is the wavelength of an operating frequency of the planar antenna; a first radiating unit provided on the substrate unit and disposed adjacent to and spaced apart from the first feeding segment of the feeding line; a second radiating unit provided on the substrate unit and disposed adjacent to and spaced apart from the second feeding segment of the feeding line; and a grounding unit provided on the substrate unit for grounding.06-03-2010

Chia-Ling Lu, Luzhou City TW

Patent application numberDescriptionPublished
20100109043METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.05-06-2010
20100109076STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.05-06-2010
20110216454ELECTROSTATIC DISCHARGE PROTECTORS HAVING INCREASED RC DELAYS - An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.09-08-2011

Chia-Ling Lu, Taipei TW

Patent application numberDescriptionPublished
20110204447ESD TOLERANT I/O PAD CIRCUIT INCLUDING A SURROUNDING WELL - An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.08-25-2011

Chia-Ling Wei, Tainan TW

Patent application numberDescriptionPublished
20080234588Method and Apparatus for Determining Cardiac Performance in a Patient with a Conductance Catheter - An apparatus for determining cardiac performance in the patient involving a conductance catheter (09-25-2008
20110196250Method and apparatus for determining cardiac performance in a patient with a conductance catheter - An apparatus for determining cardiac performance in the patient. The apparatus includes a conductance catheter for measuring conductance and blood volume in a heart chamber of the patient. The apparatus includes a processor for determining instantaneous volume of the ventricle by applying a non-linear relationship between the measured conductance and the volume of blood in the heart chamber to identify mechanical strength of the chamber. The processor is in communication with the conductance catheter. Methods for determining cardiac performance in a patient. Apparatuses for determining cardiac performance in a patient.08-11-2011

Chia-Ling Wu, Taipei TW

Patent application numberDescriptionPublished
20110100452SOLAR ENERGY COLLECTOR AND METHOD OF MANUFACTURING THE SAME - A solar energy collector and a method for manufacturing the same. The solar energy collector has a solar chip, conductive wires connected to the solar chip, and a securing line that secures the solar chip and the conductive wires. The solar energy collector is rollable, foldable and expandable.05-05-2011

Chia-Ling Yang, Taipei TW

Patent application numberDescriptionPublished
20090243372HUB INSTALLED TO A BICYCLE - A hub installed to a bicycle is disclosed. The normal force of each rolling ball set and the spindle has an inclined angle so that the bearing can suffer from a greater axial force so as to increase the lifetime of the hub. The sizes of the rolling balls are enlarged and the number of the rolling balls used is increased. The annular rib is integrally formed with the hub so as to increase the concentricity between the hub body and the ratchet wheel. The swing range of the hub is decreased and thus it is smooth. The first resisting portion, second resisting portion, seven resisting portion and eight resisting portion are matched to cambered recesses of the first rolling ball set, second rolling ball set, third rolling ball set, and fourth rolling ball set so that the resisting areas between the rolling balls and the resisting portions are increased.10-01-2009