| Patent application number | Description | Published |
|---|
| 20080252373 | Low Flicker Noise Operational Amplifier - A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal. | 10-16-2008 |
| 20080268805 | High Linearity Passive Mixer and Method Thereof - A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit. | 10-30-2008 |
| 20090029668 | LOW FLICKER NOISE ACTIVE MIXER AND METHOD THEREOF - A low flicker noise active mixer comprises a trans-conductance section, a switching quad, and a load section. The trans-conductance section converts a voltage signal pair into a first current signal pair. The switching quad converts the first current signal pair into a second signal pair in a manner controlled by a LO (local oscillator) signal pair. The load section provides a loading to the second current signal pair using a pair of commutative active loads to convert the second current signal pair into an output voltage signal pair. | 01-29-2009 |
| 20090073012 | SELF-CALIBRATING DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - A digital-to-analog converter improves differential non-linearity by performing a calibration of at least one weighted cell in response to a calibration command. The digital-to-analog converter includes a group of weighted cells, a tunable cell having a tunable weight controlled by a tuning word, and a calibration cell to generate a combined output signal in response to a digital input word, the calibration command, and a calibration sequence. The digital-to-analog converter also includes a calibration circuit configured to sample and subsequently process the combined output signal to establish the tuning word in accordance with the calibration command and the calibration sequence. | 03-19-2009 |
| 20090074125 | TIME-INTERLEAVED CLOCK-DATA RECOVERY AND METHOD THEREOF - A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit. | 03-19-2009 |
| 20090085681 | HIGH-RESOLUTION DIGITALLY CONTROLLED OSCILLATOR AND METHOD THEREOF - A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word. | 04-02-2009 |
| 20090163166 | PHASE LOCK LOOP WITH PHASE INTERPOLATION BY REFERENCE CLOCK AND METHOD FOR THE SAME - The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer. | 06-25-2009 |
| 20090206962 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 08-20-2009 |
| 20090231050 | DIGITAL FRACTIONAL-N PHASE LOCK LOOP AND METHOD THEREOF - A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number. | 09-17-2009 |
| 20090261878 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier. | 10-22-2009 |
| 20090267668 | METHOD AND APPARATUS FOR CALIBRATING A DELAY CHAIN - Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed. | 10-29-2009 |
| 20090267698 | DUAL SUPPLY INVERTER FOR VOLTAGE CONTROLLED RING OSCILLATOR - A voltage controlled ring oscillator reduces sensitivity of an oscillation frequency to a control voltage by using a dual supply inverter logic circuit. The dual supply inverter logic circuit includes two inverter circuits coupled in parallel between an input terminal and an output terminal. The first inverter circuit is powered by a variable supply voltage while the second inverter circuit is powered by a substantially fixed supply voltage. The variable supply voltage serves as the control voltage for the voltage controlled ring oscillator and sets the oscillation frequency. The sensitivity of the oscillation frequency to changes in the variable supply voltage is reduced due to the parallel connection of the second inverter circuit powered by a different supply voltage. | 10-29-2009 |
| 20090323566 | ALL-DIGITAL TIMING CONTROL FOR MULTI-CHANNEL FULL-DUPLEX TRANSCEIVER - A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a symbol-rate-converters for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals. | 12-31-2009 |
| 20100086090 | CLOCK-DATA RECOVERY AND METHOD FOR BINARY SIGNALING USING LOW RESOLUTION ADC - A binary signal detection based on low resolution ADC includes: a variable-gain amplifier for amplifying an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an ADC for converting the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit for generating a timing error signal based on the converter output; a filter for filtering the timing error signal to generate a control signal; a controllable oscillator for generating the recovered clock under a control of the control voltage; an automatic gain control for processing the converter data to set the gain setting to control the gain factor; and a data recovery circuit for generate a recovered data based on the converter output. | 04-08-2010 |
| 20100225513 | Self-Calibrating Pipeline ADC and Method Thereof - An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation. | 09-09-2010 |
| 20100259324 | BROAD-BAND ACTIVE DELAY LINE - A broad-band active delay line comprises a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell comprises a feedback loop and a feedforward path to achieve a high bandwidth. | 10-14-2010 |
| 20100262640 | HIGH-SPEED CONTINUOUS-TIME FIR FILTER - A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path. | 10-14-2010 |
| 20110012683 | METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE - a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. | 01-20-2011 |
| 20110089988 | Self-Calibrating R-2R Ladder and Method Thereof - A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N−1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word. When the first logical signal is 0, the apparatus operates in a normal mode and the output signal follows the N control bits; when the first logical signal is 1, the apparatus operates in a calibration mode and the output signal follows the second logical signal. When the apparatus operates in the calibration mode, the tuning word is adjusted in a closed loop manner so as to make the output signal substantially the same regardless of a value of the second logical signal. | 04-21-2011 |
| 20110140676 | Mismatch-Free Charge Pump and Method Thereof - The charge-pump apparatus is disclosed having a substantially fixed current source for outputting a first current of a first polarity; a variable current source for outputting a second current of a second polarity opposite to the first polarity; a first current steering network for steering the first current into either an output node or a termination node in accordance with a first control signal; a second current steering network for steering the second current into either the output node or the termination node in accordance with a second control signal; a voltage follower for receiving a first voltage associated with the output node and outputting a second voltage at an internal node; a current sensor inserted between the termination node and the internal node for sensing a current flowing between the termination node and the internal node; and a feedback network for adjusting the variable current source in accordance with an output of the current sensor. | 06-16-2011 |
| 20110140767 | Method and Apparatus for Charge Leakage Compensation for Charge Pump with Leaky Capacitive Load - An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed. | 06-16-2011 |
| 20110163828 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 07-07-2011 |
