Patent application number | Description | Published |
20080252373 | Low Flicker Noise Operational Amplifier - A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal. | 10-16-2008 |
20080268805 | High Linearity Passive Mixer and Method Thereof - A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit. | 10-30-2008 |
20090029668 | LOW FLICKER NOISE ACTIVE MIXER AND METHOD THEREOF - A low flicker noise active mixer comprises a trans-conductance section, a switching quad, and a load section. The trans-conductance section converts a voltage signal pair into a first current signal pair. The switching quad converts the first current signal pair into a second signal pair in a manner controlled by a LO (local oscillator) signal pair. The load section provides a loading to the second current signal pair using a pair of commutative active loads to convert the second current signal pair into an output voltage signal pair. | 01-29-2009 |
20090073012 | SELF-CALIBRATING DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - A digital-to-analog converter improves differential non-linearity by performing a calibration of at least one weighted cell in response to a calibration command. The digital-to-analog converter includes a group of weighted cells, a tunable cell having a tunable weight controlled by a tuning word, and a calibration cell to generate a combined output signal in response to a digital input word, the calibration command, and a calibration sequence. The digital-to-analog converter also includes a calibration circuit configured to sample and subsequently process the combined output signal to establish the tuning word in accordance with the calibration command and the calibration sequence. | 03-19-2009 |
20090074125 | TIME-INTERLEAVED CLOCK-DATA RECOVERY AND METHOD THEREOF - A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit. | 03-19-2009 |
20090085681 | HIGH-RESOLUTION DIGITALLY CONTROLLED OSCILLATOR AND METHOD THEREOF - A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word. | 04-02-2009 |
20090163166 | PHASE LOCK LOOP WITH PHASE INTERPOLATION BY REFERENCE CLOCK AND METHOD FOR THE SAME - The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer. | 06-25-2009 |
20090206962 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 08-20-2009 |
20090231050 | DIGITAL FRACTIONAL-N PHASE LOCK LOOP AND METHOD THEREOF - A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number. | 09-17-2009 |
20090261878 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier. | 10-22-2009 |
20090267668 | METHOD AND APPARATUS FOR CALIBRATING A DELAY CHAIN - Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed. | 10-29-2009 |
20090267698 | DUAL SUPPLY INVERTER FOR VOLTAGE CONTROLLED RING OSCILLATOR - A voltage controlled ring oscillator reduces sensitivity of an oscillation frequency to a control voltage by using a dual supply inverter logic circuit. The dual supply inverter logic circuit includes two inverter circuits coupled in parallel between an input terminal and an output terminal. The first inverter circuit is powered by a variable supply voltage while the second inverter circuit is powered by a substantially fixed supply voltage. The variable supply voltage serves as the control voltage for the voltage controlled ring oscillator and sets the oscillation frequency. The sensitivity of the oscillation frequency to changes in the variable supply voltage is reduced due to the parallel connection of the second inverter circuit powered by a different supply voltage. | 10-29-2009 |
20090323566 | ALL-DIGITAL TIMING CONTROL FOR MULTI-CHANNEL FULL-DUPLEX TRANSCEIVER - A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a symbol-rate-converters for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals. | 12-31-2009 |
20100086090 | CLOCK-DATA RECOVERY AND METHOD FOR BINARY SIGNALING USING LOW RESOLUTION ADC - A binary signal detection based on low resolution ADC includes: a variable-gain amplifier for amplifying an input signal with a gain factor controlled by a gain setting to generate an amplified signal; an ADC for converting the amplified signal into a converter output in accordance with a timing provided by a recovered clock, wherein the converter output has N levels; a timing detection circuit for generating a timing error signal based on the converter output; a filter for filtering the timing error signal to generate a control signal; a controllable oscillator for generating the recovered clock under a control of the control voltage; an automatic gain control for processing the converter data to set the gain setting to control the gain factor; and a data recovery circuit for generate a recovered data based on the converter output. | 04-08-2010 |
20100225513 | Self-Calibrating Pipeline ADC and Method Thereof - An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation. | 09-09-2010 |
20100259324 | BROAD-BAND ACTIVE DELAY LINE - A broad-band active delay line comprises a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell comprises a feedback loop and a feedforward path to achieve a high bandwidth. | 10-14-2010 |
20100262640 | HIGH-SPEED CONTINUOUS-TIME FIR FILTER - A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path. | 10-14-2010 |
20110012683 | METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE - a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. | 01-20-2011 |
20110089988 | Self-Calibrating R-2R Ladder and Method Thereof - A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N−1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word. When the first logical signal is 0, the apparatus operates in a normal mode and the output signal follows the N control bits; when the first logical signal is 1, the apparatus operates in a calibration mode and the output signal follows the second logical signal. When the apparatus operates in the calibration mode, the tuning word is adjusted in a closed loop manner so as to make the output signal substantially the same regardless of a value of the second logical signal. | 04-21-2011 |
20110140676 | Mismatch-Free Charge Pump and Method Thereof - The charge-pump apparatus is disclosed having a substantially fixed current source for outputting a first current of a first polarity; a variable current source for outputting a second current of a second polarity opposite to the first polarity; a first current steering network for steering the first current into either an output node or a termination node in accordance with a first control signal; a second current steering network for steering the second current into either the output node or the termination node in accordance with a second control signal; a voltage follower for receiving a first voltage associated with the output node and outputting a second voltage at an internal node; a current sensor inserted between the termination node and the internal node for sensing a current flowing between the termination node and the internal node; and a feedback network for adjusting the variable current source in accordance with an output of the current sensor. | 06-16-2011 |
20110140767 | Method and Apparatus for Charge Leakage Compensation for Charge Pump with Leaky Capacitive Load - An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed. | 06-16-2011 |
20110163828 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 07-07-2011 |
20110182390 | Methods and Apparatuses of Serial Link Transceiver Without External Reference Clock - A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted. | 07-28-2011 |
20110234273 | METHOD AND APPARATUS FOR CHARGE LEAKAGE COMPENSATION FOR CHARGE PUMP - An apparatus is disclosed, the apparatus comprising: a charge pump for receiving a phase signal representing a result of a phase detection and for outputting a current flowing between an internal node and an output node; a capacitive load shunt at the output node; a current source controlled by a bias voltage for outputting a compensation current to the internal node; a current sensor inserted between the internal node and the output node for sensing the current; and a feedback network for adjusting the bias voltage in accordance with an output of the current sensor. | 09-29-2011 |
20110235695 | HIGH-SPEED CONTINUOUS-TIME FEEDBACK EQUALIZER FOR SERIAL LINK RECEIVER - An apparatus is disclosed, the apparatus comprising: a broad-band continuous-time adjustable weight summing cell for summing an input signal and a feedback signal into an intermediate signal in accordance with a weight factor for the feedback signal; a broad-band continuous-time delay cell for receiving the intermediate signal and outputting the feedback signal; a broad-band variable gain amplifier for amplifying the feedback signal into an output signal in accordance with a gain factor; and an adaptation circuit for adjusting the weight and the gain factor in accordance with the output signal and a timing defined by a clock signal so as to minimize an interference form a previous data to a present data embedded in the output signal. | 09-29-2011 |
20110254631 | REFERENCE ASSISTED CONTROL SYSTEM AND METHOD THEREOF - A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal. | 10-20-2011 |
20110254633 | METHOD AND APPARATUS FOR ALLEVIATING CHARGE LEAKAGE OF VCO FOR PHASE LOCK LOOP - Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit. | 10-20-2011 |
20110316600 | Serial Link Receiver and Method Thereof - A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision. | 12-29-2011 |
20120043959 | Received Signal Strength Indicator and Method Thereof - An apparatus includes a PMOS (p-channel metal-oxide semiconductor) transistor, a NMOS (n-channel metal-oxide semiconductor) transistor, a first capacitor, and a second capacitor, wherein: a first terminal of the PMOS transistor is coupled to a first signal; a second terminal of the PMOS transistor is coupled to a second signal; a third terminal of the PMOS transistor is coupled to the first capacitor; a first terminal of the NMOS transistor is coupled to the second signal; a second terminal of NMOS transistor is coupled to the first signal; and a third terminal of the NMOS transistor is coupled to the second capacitor. | 02-23-2012 |
20120133439 | Reference Voltage Buffer and Method Thereof - An apparatus comprises: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal shunt to a ground node via a shunt capacitor; a resistor coupling the output terminal of the OTA to the feedback node; and a load circuit coupled to the feedback node via a switch controlled by a logical signal, wherein: an impedance of the shunt capacitor is substantially smaller than an input impedance of the load circuit. In an embodiment, the load circuit is a switch capacitor circuit. A corresponding method using an OTA is also provided. | 05-31-2012 |
20120139669 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 06-07-2012 |
20120229184 | All Digital Serial Link Receiver with Low Jitter Clock Regeneration and Method Thereof - An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus. | 09-13-2012 |
20130069727 | Transimpedance Amplifier and Method Thereof - A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node. | 03-21-2013 |
20130076439 | Limiting Amplifier And Method Thereof - A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner. | 03-28-2013 |
20130106515 | METHOD AND APPARATUS OF COMMON MODE COMPENSATION FOR VOLTAGE CONTROLLED DELAY CIRCUITS | 05-02-2013 |
20130106516 | Fast Settling Reference Voltage Buffer and Method Thereof | 05-02-2013 |
20130106525 | SINGLE-STAGED BALANCED-OUTPUT INDUCTOR-FREE OSCILLATOR AND METHOD THEREOF | 05-02-2013 |
20130128642 | Signal Level Detector and Method Thereof - A signal level detector and detecting method are provided. In one implementation a method includes receiving a differential input signal; incorporating two configurable rectifiers of the same circuit topology; configuring a first one of the two configurable rectifiers as a inverting rectifier to generate an inverting end of an output signal in response to an absolute value of the differential input signal; and configuring a second one of the two configurable rectifiers as a non-inverting rectifier to generate a non-inverting end of the output signal. | 05-23-2013 |
20130162454 | HIGH-SPEED SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data. | 06-27-2013 |
20130177325 | Method and Apparatus of Automatic Power Control for Burst Mode Laser Transmitter - An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: generating an output current with a modulation pattern determined by a transmit data and a transmit enable signal, and a modulation level determined by a first control code and a second control code, wherein a light signal is generated in response to the output current; generating a first decision based on a comparison between a photodiode current and the first reference current, a second decision based on a comparison between the photodiode current and the second reference current, wherein the photodiode current is generated in accordance to the light signal; and generating the first control code and the second control code in response to the first decision and the second decision. | 07-11-2013 |
20130194040 | Limiting Amplifier And Method Thereof - A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage. | 08-01-2013 |
20130222023 | DIGITAL PHASE LOCK LOOP AND METHOD THEREOF - An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code. | 08-29-2013 |
20130249506 | Integrated Switch-Capacitor DC-DC Converter and Method Thereof - An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks. | 09-26-2013 |
20140035767 | Successive-Approximation-Register Analog-to-Digital Converter and Method Thereof - A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. | 02-06-2014 |
20150061787 | METHOD AND APPARATUS FOR SUPPRESSING A DETERMINISTIC CLOCK JITTER - A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal. | 03-05-2015 |
20150069838 | Integrated Switch-Capacitor DC-DC Converter and Method Thereof - An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks. | 03-12-2015 |