Patent application number | Description | Published |
20100141147 | CAPACITIVELY COUPLED PLASMA (CCP) GENERATOR WITH TWO INPUT PORTS - A capacitively coupled plasma (CCP) generator with two input ports, which is especially used as a large-area capacitively coupled plasma (CCP) generator. In the inventive CCP generator, only a RF power supply is required to provide the two input ports with RF power. The input impedance at each of the input ports is adjustable so that the standing wave between two rectangular electrodes can be eliminated to achieve plasma uniformity. | 06-10-2010 |
20110136269 | METHOD FOR DEPOSITING MICROCRYSTALLINE SILICON AND MONITOR DEVICE OF PLASMA ENHANCED DEPOSITION - A method for depositing a microcrystalline silicon film is disclosed, including performing an open loop and close loop plasma enhanced deposition process without and with modulating process parameters, respectively. A film is deposited by the open loop plasma enhanced deposition process till a required film crystallinity and then performing a closed loop plasma enhanced deposition process which monitors species plasma spectrum intensities SiH* and Hα and modulates process parameters of the plasma enhanced deposition process resulting in the species concentration stabilization which controls the intensities variation of SiH* and Hα within an allowed range of a target value for improving film depositing rate. | 06-09-2011 |
20110273902 | BACKLIGHT MODULE - A backlight module includes a light guide plate and at least one light source. The light guide plate has a first light-emitting surface, a second light-emitting surface opposite the first light-emitting surface, and at least one side surface connected between the first light-emitting surface and the second light-emitting surface. The light guide plate has a first substance and a second substance surrounding the first substance, and the second substance is different to the first substance to form at least a first light reflecting/diffusing interface and a second light reflecting/diffusing interface. A light beam emitted by the light source is deflected by the first light reflecting/diffusing interface and output via the first light-emitting surface, and a light beam emitted by the light source is deflected by the second light reflecting/diffusing interface and output via the second light-emitting surface. | 11-10-2011 |
20120170261 | LIGHT SOURCE MODULE - A light source module includes a base, a positioning member, a LED light bar having a first electrical contact, and a circuit board having a second electrical contact. The positioning member is mounted on the base and has a first slot and a second slot. The LED light bar is inserted into the first slot and capable of being extracted from the first slot. The circuit board is inserted into the second slot and capable of being extracted from the second slot. The LED light bar is electrically connected to the circuit board via the first electrical contact and the second electrical contact when the LED light bar and the circuit board are respectively inserted into the first slot and the second slot. | 07-05-2012 |
20120182762 | ILLUMINATION MODULE - An illuminating module includes at least one light-emitting chip, a phosphor, and a color temperature conversion media. The light-emitting chip is capable of emitting wavelength light, and the phosphor is disposed in a propagation path of the wavelength light to transform the wavelength light into a first white light with a first color temperature. The color temperature conversion media is disposed in a propagation path of the first white light to transform the first white light into a second white light with a second color temperature. The second color temperature is smaller than the first color temperature. | 07-19-2012 |
20120292687 | SUPER JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit. | 11-22-2012 |
20130043528 | Power transistor device and fabricating method thereof - The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer. | 02-21-2013 |
20130082324 | LATERAL STACK-TYPE SUPER JUNCTION POWER SEMICONDUCTOR DEVICE - A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure. | 04-04-2013 |
20130105891 | POWER TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF | 05-02-2013 |
20130119460 | TRENCH TYPE POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF - The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region. | 05-16-2013 |
20130130485 | METHOD FOR FABRICATING SCHOTTKY DEVICE - A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer. | 05-23-2013 |
20130134487 | POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type. | 05-30-2013 |
20130153994 | TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 06-20-2013 |
20130164915 | METHOD FOR FABRICATING POWER SEMICONDUCTOR DEVICE WITH SUPER JUNCTION STRUCTURE - A method for fabricating a power semiconductor device is provided. A substrate with a first conductivity type is prepared. A semiconductor layer with a second conductivity type is formed on the substrate. A hard mask pattern having at least an opening is formed on the semiconductor layer. A first trench etching is performed to form a first recess in the semiconductor layer via the opening. A first ion implantation is performed to vertically implant dopants into the bottom of the first recess via the opening, thereby forming a first doping region. A second trench etching is performed to etch through the first doping region, thereby forming a second recess. | 06-27-2013 |
20130203229 | METHOD OF REDUCING SURFACE DOPING CONCENTRATION OF DOPED DIFFUSION REGION, METHOD OF MANUFACTURING SUPER JUNCTION USING THE SAME AND METHOD OF MANUFACTURING POWER TRANSISTOR DEVICE - The present invention provides a method of reducing a surface doping concentration of a doped diffusion region. First, a semiconductor substrate is provided. The semiconductor substrate has the doped diffusion region disposed therein, and the doped diffusion region is in contact with a surface of the semiconductor substrate. A doping concentration of the doped diffusion region close to the surface is larger than a doping concentration of the doped diffusion region away from the surface. Then, a thermal oxidation process is performed to form an oxide layer on the surface of the semiconductor substrate. A part of the doped diffusion region in contact with the surface reacts with oxygen to form a part of the oxide layer. Then, the oxide layer is removed. | 08-08-2013 |
20130210205 | MANUFACTURING METHOD OF POWER TRANSISTOR DEVICE WITH SUPER JUNCTION - The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench. | 08-15-2013 |
20130252408 | METHOD FOR FABRICATING SCHOTTKY DEVICE - A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer. | 09-26-2013 |
20130292760 | POWER TRANSISTOR DEVICE - The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region. | 11-07-2013 |
20130307064 | POWER TRANSISTOR DEVICE AND FABRICATING METHOD THEREOF - The present invention provides a power transistor device including a substrate, a first epitaxial layer, a doped diffusion region, a second epitaxial layer, a doped base region, and a doped source region. The substrate, the first epitaxial layer, the second epitaxial layer and the doped source region have a first conductive type, and the doped diffusion region and the doped base region have a second conductive type. The first epitaxial layer and the second epitaxial layer are sequentially disposed on the substrate, and the doped diffusion region is disposed in the first epitaxial layer. The doped base region is disposed in the second epitaxial layer and contacts the doped diffusion region, and the doped source region is disposed in the doped base region. A doping concentration of the second epitaxial layer is less than a doping concentration of the first epitaxial layer. | 11-21-2013 |
20140015040 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a substrate, a semiconductor layer grown on the substrate, a plurality of alternately arranged first conductivity type doping trenches and second conductivity type doping trenches in the semiconductor substrate, a first diffusion region of the first conductivity type around each of the first conductivity type doping trenches, and a second diffusion region of the second conductivity type around each of the second conductivity type doping trenches, wherein distance between an edge of the first conductivity type doping trench and PN junction between the first and second diffusion regions substantially equals to a distance between an edge of the second conductivity type doping trench and the PN junction. | 01-16-2014 |
20140051220 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench. | 02-20-2014 |
20140065795 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 03-06-2014 |
20140087540 | METHOD FOR FORMING TRENCH ISOLATION - A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench. | 03-27-2014 |
20140099762 | MANUFACTURING METHOD OF TRENCH TYPE POWER TRANSISTOR DEVICE WITH SUPER JUNCTION - The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate. | 04-10-2014 |
20140197478 | POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type. | 07-17-2014 |
20140199816 | METHOD OF FABRICATING A SUPER JUNCTION TRANSISTOR - A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed. | 07-17-2014 |
20140291773 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another. | 10-02-2014 |
20140327039 | TRENCH TYPE POWER TRANSISTOR DEVICE - The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region. | 11-06-2014 |
20140342517 | METHOD FOR FABRICATING TRENCH TYPE POWER SEMICONDUCTOR DEVICE - A method of forming a trench type semiconductor power device is disclosed. An epitaxial layer is formed on a substrate. A gate trench is formed in the epitaxial layer. A gate oxide layer and a trench gate are formed in the gate trench. A source region is then formed in the epitaxial layer. A dielectric layer is then deposited in a blanket manner. A contact hole is then formed in the dielectric layer and the epitaxial layer. A base ion implantation is then carried out to form at least one doping region in the epitaxial layer through the contact hole. A contact hole implantation process is then performed to form a contact doping region at the bottom of the contact hole. | 11-20-2014 |
20150054062 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another. | 02-26-2015 |