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Chia-Cheng
Chia-Cheng Chang, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090103300 | LAMP STRUCTURE WITH LOW TEMPERATURE FEATURE - A fluorescent lamp holder combination device includes a main lamp holder and an auxiliary lamp holder set, which is provided with an auxiliary lamp holder. The main lamp holder is internally configured with a multifunction ballast, which is electrically connected to a conducting portion. Each of the conducting portions is electrically connected to a connecting portion of each of the auxiliary lamp holders by means of a set of conducting cables, thereby enabling parallel connection between each of the auxiliary lamp holders using the single multifunction ballast, and achieving the effectiveness to enable the single multifunction ballast to provide stable rectification and energy saving for the auxiliary lamp holders. Furthermore, a starting capacitor and current-limiting inductor can be disposed within each of the auxiliary lamp holders, thereby reducing use-cost of the set of conducting cables while facilitating maintenance of the starting capacitors and the current-limiting inductors. | 04-23-2009 |
Chia-Cheng Chang, Yuanlin Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110213114 | DENDRON, POLYURETHANE WITH SIDE-CHAIN REGULAR DENDRON, AND PRODUCING METHODS THEREOF - A dendron with hydrophobic functional of end group, a polyurethane with the dendron, and producing methods thereof are disclosed. The dendron with hydrophobic functional of end group in the polyurethane systems, and the honeycomb-like structure thin films were obtained by a breath-figure process. The structures of dendron and dendritic side-chain polyurethanes are respectively expressed in the following. Therein, the end-groups (R) of the dendron are long alkyl chains or perfluoroalkyl derivatives. | 09-01-2011 |
Chia-Cheng Chang, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090032288 | CONNECTOR AND PRINTED CIRCUIT BOARD - A connector including a first pin and a second pin is disclosed. The first pin includes a first side including a first protrudent part. The second pin includes a second side facing the first side. The first protrudent part approaches the second side. | 02-05-2009 |
| 20090035968 | Connector and printed circuit board - A connector including a first pin and a second pin is disclosed. The first pin includes a first side including a first protrudent part. The second pin includes a second side facing the first side. The first protrudent part approaches the second side. | 02-05-2009 |
Chia-Cheng Chen, Taichung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT - A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage. | 11-10-2011 |
| 20120008377 | STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY - A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit. | 01-12-2012 |
| 20120008449 | LOW POWER STATIC RANDOM ACCESS MEMORY - A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices. | 01-12-2012 |
Chia-Cheng Chen, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120033522 | VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY - A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM. | 02-09-2012 |
Chia-Cheng Chen, Madou Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
Chia-Cheng Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120015503 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate. | 01-19-2012 |
Chia-Cheng Chou, Keelung TW
| Patent application number | Description | Published |
|---|---|---|
| 20080311756 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 12-18-2008 |
Chia-Cheng Chou, Keelung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080272493 | Semiconductor device - A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer. | 11-06-2008 |
| 20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
| 20090286394 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 11-19-2009 |
| 20110217840 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 09-08-2011 |
| 20110263127 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 10-27-2011 |
Chia-Cheng Kuo, Yilan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100063620 | AUTOMATED MATERIAL HANDLING SYSTEM AND METHOD - An automated material handling system for combining over-head conveyer with a material control system is disclosed. First and second virtual stocker codes are respectively assigned to first and second virtual stocker of an over-head conveyer (OHC) using a material control system. A front opening unified pod (FOUP) is moved to and loaded in the first virtual stocker using a transport system controller. The FOUP is loaded in a track of the OHC and assigned a virtual vehicle code. The FOUP is moved, along the track, to the second virtual stocker and loaded in the second virtual stocker, while the virtual vehicle code is being removed, and is removed therefrom using the transport system controller. | 03-11-2010 |
Chia-Cheng Lee, Sanchong City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100225234 | Hollow-cathode plasma generator - A hollow-cathode plasma generator includes a plurality of hollow cathodes joined together and connected to a power supply for generating plasma in vacuum. Each of the hollow cathodes includes at least one fillister defined therein, a fin formed on a side of the fillister, an air-circulating tunnel in communication with the fillister and a coolant-circulating tunnel defined therein. The fillister is used to contain working gas. The fin receives negative voltage from the power supply for ionizing the working gas to generate the plasma and spread the plasma in a single direction. The working gas travels into the fillister from the air-circulating tunnel. The coolant-circulating tunnel is used to circulate coolant for cooling the hollow cathode. | 09-09-2010 |
Chia-Cheng Lin, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110095998 | EXTERNAL INPUT DEVICE - An external input device is disclosed. The external input device comprises an upper case, a touch sensor module, a control module, a lighting module, a transfer module, a transparent substrate, and a lower case. The upper case comprises a visible region and a shielding region; the touch sensor module is provided under the upper case; control module is provided under the shielding region; the lighting module is provided on the control module; the transparent substrate is provided under the touch sensor; and the lower case is used for sitting the touch sensor module, the control module, the lighting module, the transfer module, and transparent substrate, and integrates with the upper case. The external input device can be used for performing pointing mode and key-in mode to replace the functions of mice, touch panel, and partial functions of keyboards, and the external input device is easy to switch between the modes for users. | 04-28-2011 |
Chia-Cheng Liu, Hsichih TW
| Patent application number | Description | Published |
|---|---|---|
| 20090080538 | Method and Apparatus for Decoding a Video Signal - An apparatus for transmitting a video signal has a receiver, a processor and a multiplexer. The receiver receives the video signal and separates a composite sync signal from the video signal. The processor generates a vertical sync signal and a selecting signal with reference to timing characteristics of the composite sync signal. The multiplexer generates a horizontal sync signal by selectively outputting the composite sync signal when the selecting signal is at a first logic level and outputting a reference signal when the selecting signal is at a second logic level. A method for transmitting a video signal is also disclosed. | 03-26-2009 |
Chia-Cheng Yang US
| Patent application number | Description | Published |
|---|---|---|
| 20120007431 | POWER SUPPLY HAVING CONVERTERS WITH SERIALLY CONNECTED INPUTS AND PARALLEL CONNECTED OUTPUTS - A power supply is coupled to an input voltage source. The power supply includes a plurality of converters. Each converter has an input for receiving an input voltage and an output for providing an output voltage. The inputs are connected in series and the outputs are connected in parallel to provide an output voltage. The power supply further includes an output regulating controller coupled to one of the plurality of converters for regulating the output voltage. The power supply further includes one or more input regulating controllers correspondingly coupled to the remaining one or more converters of the plurality of converters for regulating one or more input voltages. | 01-12-2012 |