| Patent application number | Description | Published |
|---|
| 20080250180 | USB peripheral device with dynamic modification class and operation method of the same - A USB peripheral device with dynamic modification class is connected to a basic system of processor through a USB transmission interface. The USB peripheral device contains a card connection unit and a USB microprocessor. By judging whether the card connection unit is inserted with a card device, the USB microprocessor is determined to transmit the data or not with the basic system of processor. If one card device is inserted into the card connection unit, the USB microprocessor outputs the corresponding class code according to the device class of the card device for the basic system of processor distinguishing and confirming said class code. Therefore, dynamically changing the device class in accordance with various card devices is achieved. | 10-09-2008 |
| 20080278212 | DC OFFSET CANCELING CIRCUIT - The present invention provides a circuit for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value. | 11-13-2008 |
| 20080298223 | PACKET DETECTING CIRCUIT AND METHOD THEREOF - A packet detecting circuit detects a packet inputting time via calculating a delay correlation function and an autocorrelation function. In order to prevent a DC offset from affecting the calculation of the delay correlation function and the autocorrelation function, when the packet detecting circuit calculates the delay correlation function and the autocorrelation function, the packet detecting circuit will calculate and remove the error of the delay correlation function and the autocorrelation function produced by a DC offset. Then the packet detecting circuit calculates a packet triggering value according to the delay correlation function and the autocorrelation function for detecting the packet inputting time more precisely. | 12-04-2008 |
| 20080298266 | METHOD AND SYSTEM FOR ASSESSING STATUSES OF CHANNELS - An assessment system classifies a plurality of channels to several channel groups according to the characteristics of the channel groups and assesses the status of each channel by a corresponding method, such as a period comparison method or a SNR comparison method, defined based on the channel groups. Hence, the present invention allows simpler computations to be made and a simpler circuit structure to be used. | 12-04-2008 |
| 20090014521 | CARD READER - A card reader that can enhance the efficiency of the application system is embedded in the application system. The application system has an external memory drive. The card reader includes at least one memory card connector, a flash memory, and a control unit. The memory card connector is used for being plugged with a memory card. The flash memory is driven and integrated by the external memory drive. The control unit is electrically connected with the memory card connector and the flash memory and is used for transmitting data between the memory card and the flash memory and the application system via the control unit. Thereby, the flash memory can be used as an extended memory of the application system. The total memory of the application system increases, and the efficiency of the application system is enhanced. | 01-15-2009 |
| 20090061804 | Frequency synthesizer applied to a digital television tuner - A frequency synthesizer applied to a digital television tuner includes: a voltage controlled oscillator (VCO), a phase locked loop (PLL), a frequency divider unit, and a multiplexer. The maximum oscillated frequency of the VCO is twice its minimum frequency. The PLL controls and locks the VCO output frequency by a frequency control signal. The frequency divider unit includes a plurality of first dividers which form a cascade connection. The frequency divider unit receives the VCO output frequency, and subsequently divides the output frequency one by one. The multiplexer receives the dividing signals, and then chooses one of the dividing signals by a frequency selection signal, and generates a local oscillation signal. Hence, the present invention can implement the frequency synthesizer by simple architecture and cover the frequency ranges of Digital Video Broadcasting standard. | 03-05-2009 |
| 20090092179 | Method and a circuit for estimating the signal quality of a communication channel and a wireless receiving apparatus using the same - A method for estimating the signal quality of a communication channel is disclosed. Firstly, an input signal passes through a match filter at the initial stage of an estimation period. Next, the output of the match filter is calculated to obtain the noise reference value within a pre-determined period. The output value of the match filter and the noise reference value are compared. When the output value of the match filter is larger than the noise reference value, a valid power value is obtained according to the output value of the match filter. The valid power values are accumulated. Finally, a SNR is calculated according to the noise reference value and the accumulated valid power value at the end of the estimation period. Thereby, the signal quality of the wireless communication channel is estimated according to the SNR, and the signal transmission rate is determined. | 04-09-2009 |
| 20090135978 | Apparatus and method for estimating and compensating sampling frequency offset - An apparatus and method for estimating and compensating sampling frequency offset are disclosed. Particularly, a linear mathematical scheme is employed to calculate the related phase difference for saving use of multipliers and storage circuit used for sampling frequency offset estimation and compensation in the conventional art. The preferred embodiment of the invention has a first step to receive signals by the offset estimating circuit. Next, the phase value for each signal is calculated, and the pilot signal therein is retrieved. Next, a phase difference is obtained by subtraction operation between the received symbols and the delayed pilot symbols. And a circuit for storing the phase differences is incorporated. Next, a phase difference between the adjacent symbols is obtained by accumulating the phases and processing the least-error-sum-of-squares operation. Therefore, an estimation value of the sampling frequency offset of a communication system is obtained, and further to compensate the offset. | 05-28-2009 |
| 20090154618 | Device and method for calculating Channel State Information - Device and method for calculating channel state information (CSI) are disclosed. The device and method are applied to calculate the channel state information of a dual-carrier modulation system. When a channel equalization value is transmitted into this system, an absolute-value computing unit computes the absolute value for each equalization value. The absolute-value computing unit is electrically connected to a channel classifying unit that is used to separate signals to two channels. Every channel is connected to the equalization-value comparing unit. One smaller value resulted from a comparison operation is employed as the new-defined CSI for these two channels. Afterward, this CSI can be used in a decoder for enhancing the performance of dual-carrier modulation system in a multi-path fading channel. | 06-18-2009 |
| 20090268743 | Data transmission bridge device and control chip thereof for transmitting data - A data transmission bridge device for transmitting data that adheres to USB specification for transmitting data and includes: a first connecting interface, a second connecting interface, and a control chip. The first connecting interface is used for connecting a first host device, and the second connecting interface is used for connecting a second host device or a slave device. The control chip connects the first connecting interface and the second connecting interface, and further includes two transmission paths. The control chip detects which device is connecting to the second connecting interface, and switch to select one of the two transmission paths for transmitting data between the first connecting interface and the second connecting interface. Therefore, the present invention can achieve the purpose that the host device can bridge and transmit data with any other device conveniently. | 10-29-2009 |
| 20090289118 | Card reader integrated with touch button control and control chip module thereof - A card reader integrated with touch button control, which is applicable in an application system, the said card reader comprises: a touch sensing interface, at least a memory card interface, an interface connection unit and a control chip memory. Herein the touch sensing interface consists of plural touch buttons, and the memory card interface is used to connect a memory card. Furthermore, the interface connection unit is connected to a system connection unit of the application system; the control chip module is connected to the touch sensing interface and the memory card interface, and, in terms of the touch sensing interface and the memory card interface, respectively uses different specification of device class to build the connection with the application system in order to perform signal transmission. The card reader is thereby enabled to achieve the objectives of providing features of controlling touch buttons and accessing memory cards. | 11-26-2009 |
| 20090296723 | Multi-computer switch with function of transmitting data between computers - A multi-computer switch with a function of transmitting data between computers includes a multiple of hub units, at least one data transmission control unit and a switching interface control unit. Each hub unit includes an upstream port and a multiple of downstream ports. The upstream port is connected to a computer system, and each downstream port further includes at least one first downstream port and at least one second downstream port. The data transmission control unit is bridged to a first downstream port of any two hub units for transmitting data between computer systems connected to the two hub units according to a data exchange signal. The switching interface control unit switches and connects at least one first common peripheral to the second downstream port of one of the hub units to achieve the effect of timely transmitting data in different computers. | 12-03-2009 |
| 20100088454 | Bridging device with power-saving function - A bridging device with power-saving function includes first and second interfaces, first and second physical layer processing devices, and a controller. The first interface is utilized for coupling a first external device complying with the first interface. The first external device receives a device request signal, and accordingly sends back a device response signal through the first physical layer processing device. The second interface is utilized for coupling a second external device complying with the second interface. The controller is coupled between the first and the second physical layer processing device for transmitting the device request signal with the predetermined frequency to the first physical layer processing device in order to receive the device response signal. When the controller does not receive the device response signal, the controller turns the second physical layer processing device off. | 04-08-2010 |
| 20100096446 | ELECTRONIC STORAGE CARD READER AND CONTROL CHIP THEREOF - An electronic storage card reader applied to a computer system includes a system port, a control chip, a first card insertion part, and a second card insertion part. The system port is connected to a computer system. The control chip is connected to the system port for converting and transmitting data with the computer system. Each of the first card insertion part and the second card insertion part includes a plurality of card insertion slots connected with the control chip and provided for inserting a memory card. The control chip independently accesses the memory cards inserted into the card insertion slots of the first card insertion part, integrates the memory cards inserted into the card insertion slots of the second card insertion part to form a merged storage space, and accesses the merged storage space. The invention allows the electronic storage card reader to have a single larger storage capacity. | 04-22-2010 |
| 20110134278 | IMAGE/AUDIO DATA SENSING MODULE AND IMAGE/AUDIO DATA SENSING METHOD - An image/audio data sensing module incorporated in a case of an electronic apparatus. The image/audio data sensing module comprises: at least one image sensor, for sensing an image datum; a plurality of audio sensors, for sensing at least one audio datum; a processor, for processing the image datum and the audio datum according to a control instruction set to generate a processed image data stream and at least one processed audio data stream, and combining the processed image data stream and the processed audio data stream to generate an output data stream following a transceiver interface standard; a transceiver interface, for receiving the control instruction set and transmitting the output data stream via a multiplexing process; and a circuit board, wherein the image sensor, the audio sensors and the transceiver interface are coupled to the circuit board, and the processor is provided on the circuit board. | 06-09-2011 |
| 20110138203 | UNIVERSAL SERIAL BUS APPARATUS FOR LOWERING POWER CONSUMPTION - A universal serial bus (USB) apparatus for lowering power consumption is provided. The universal serial bus apparatus includes a universal serial bus circuitry, a monitor unit, and a system duty clock generator. The monitor unit is used to monitor a start of frame (SOF) packet generated by the universal serial bus circuitry and generates a clock control signal accordingly. The system duty clock generator receives the clock control signal and a reference clock signal to generate a system duty clock signal. The enable or disable status of the system duty clock signal can be determined according to the SOF packet monitored by the monitor unit so as to make the universal serial bus apparatus enter into runtime idle mode to lower the power consumption. | 06-09-2011 |
| 20110161545 | I2C/SPI CONTROL INTERFACE CIRCUITRY, INTEGRATED CIRCUIT STRUCTURE, AND BUS STRUCTURE THEREOF | 06-30-2011 |
