Patent application number | Description | Published |
20110068766 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator includes a proportional to absolute temperature (PTAT) current source and a voltage divider. The PTAT current source is capable of providing a first current that is proportional to a temperature. The voltage divider is capable of receiving a second current that is proportional to the first current. The voltage divider is capable of outputting a reference voltage. The reference voltage is substantially independent from a change of the temperature. | 03-24-2011 |
20110090012 | CIRCUIT AND METHOD FOR RADIO FREQUENCY AMPLIFIER - A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate. | 04-21-2011 |
20110108950 | VERTICAL METAL INSULATOR METAL CAPACITOR - A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density. | 05-12-2011 |
20110193658 | FILTER USING A WAVEGUIDE STRUCTURE - A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports. | 08-11-2011 |
20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 08-25-2011 |
20110215420 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 09-08-2011 |
20120017192 | METHOD AND APPARATUS FOR LOW POWER SEMICONDUCTOR CHIP LAYOUT AND LOW POWER SEMICONDUCTOR CHIP - A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell. | 01-19-2012 |
20120068742 | METHOD AND APPARATUS FOR EFFICIENT TIME SLICING - Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit. | 03-22-2012 |
20120092077 | CAPACITOR COUPLED QUADRATURE VOLTAGE CONTROLLED OSCILLATOR - A quadrature oscillator includes a first oscillator having a first second-order harmonic node, a second oscillator having a second second-order harmonic node, and at least one capacitor coupling the first second-order harmonic node and the second second-order harmonic node. The first oscillator is configured to supply an in-phase signal and the second oscillator is configured to supply a quadrature signal. | 04-19-2012 |
20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
20120098592 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module. | 04-26-2012 |
20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
20120262216 | UP-CONVERSION MIXER - According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum. | 10-18-2012 |
20120319176 | GATED-VARACTORS - In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region. | 12-20-2012 |
20130093504 | REFERENCE VOLTAGE GENERATORS, INTEGRATED CIRCUITS, AND METHODS FOR OPERATING THE REFERENCE VOLTAGE GENERATORS - A reference voltage generator is described. The reference voltage generator includes a proportional to absolute temperature (PTAT) current source, the PTAT current source being capable of providing a first current that is proportional to a temperature. The reference voltage generator further includes a current mirror comprising a first transistor and a second transistor, the current mirror configured to generate a second current proportional to the first current, wherein a ratio of the first current to the second current is equal to a ratio of a gate width of the first transistor to a gate width of the second transistor. The reference voltage generator further includes a voltage divider, the voltage divider being capable of receiving the second current, the voltage divider capable of outputting a reference voltage, the reference voltage being substantially independent from a change of the temperature. | 04-18-2013 |
20130120035 | LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP - A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods. | 05-16-2013 |
20130135011 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 05-30-2013 |
20130135018 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits. | 05-30-2013 |
20130147023 | INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE - The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps. | 06-13-2013 |
20130154752 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit. | 06-20-2013 |
20130241634 | RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING - An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils. | 09-19-2013 |
20130278303 | AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE - A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal. | 10-24-2013 |
20140015576 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop. | 01-16-2014 |
20140021989 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter. | 01-23-2014 |
20140029205 | Band Pass Filter for 2.5D/3D Integrated Circuit Applications - The present disclosure relates to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip comprising a plurality of capacitors embedded in a common molding compound along with a transceiver chip, and arranged within a polymer package. Ultra-thick metallization layers are disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layers also form a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area penalty as compared to conventional solutions. The band pass filter may also be coupled to a plurality of solder balls comprising a Flip Chip Ball Grid Array suitable for 2.5D and 3D integrated circuit applications. | 01-30-2014 |
20140043148 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR WIRELESS INFORMATION ACCESS THEREOF - A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure. | 02-13-2014 |
20140049309 | UP-CONVERSION MIXER HAVING A REDUCED THIRD ORDER HARMONIC - An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output. | 02-20-2014 |
20140103961 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 04-17-2014 |
20140111273 | INDUCTOR WITH CONDUCTIVE TRACE - Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure, such as a ferrite core. A molding material, such as a dielectric, is formed around the magnetic structure. A conductive trace, comprising one or more conductive pillars interconnected by one or more upper interconnects and one or more lower interconnects, is formed around the magnetic structure to form the inductor. The conductive trace allows physical limitations associated with winding a wire to be avoided, and thus allows the inductor to be smaller than wire wound inductors. In one example, the inductor is formed within an integrated circuit package comprising an active device, such as an integrated circuit. In this way, the inductor can be connected to the integrated circuit within the integrated circuit package. | 04-24-2014 |
20140183660 | POWER CELL AND POWER CELL CIRCUIT FOR A POWER AMPLIFIER - A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin. | 07-03-2014 |
20140184275 | POWER CELL, POWER CELL CIRCUIT FOR A POWER AMPLIFIER AND A METHOD OF MAKING AND USING A POWER CELL - A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer. | 07-03-2014 |
20140184296 | MCML RETENTION FLIP-FLOP/LATCH FOR LOW POWER APPLICATIONS - The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed. | 07-03-2014 |
20140203881 | Ultra-Low Voltage-Controlled Oscillator with Trifilar Coupling - The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair. A trifilar coupling network is composed of a drain inductive component, a source inductive component, and a gate inductive component for a single-ended oscillator, wherein a coupling between drain inductive components and gate inductive components between single-ended oscillators along with a negative feedback loop within each single-ended oscillator forms a cross-coupled pair of transistors which reduces the drain-to-source voltage headroom to approximately a saturation voltage of a transistor within the cross-coupled pair. Other devices and methods are also disclosed. | 07-24-2014 |
20140210528 | PHASE LOCKED LOOP (PLL) WITH MULTI-PHASE TIME-TO-DIGITAL CONVERTER (TDC) - One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal. | 07-31-2014 |
20140264745 | Transmission Line Formed Adjacent Seal Ring - An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line. | 09-18-2014 |
20140265632 | MiM CAPACITOR - One or more systems and techniques for managing one or more electronic devices are provided. A determination is made that a first capacitor in a set of one or more capacitors has a defect. Responsive to the determination, the first capacitor is disabled, and a second capacitor is enabled. | 09-18-2014 |
20140266344 | VARAINDUCTOR, VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE VARAINDUCTOR, AND PHASE LOCKED LOOP INCLUDING THE VARAINDUCTOR - A varainductor including a signal line disposed over a substrate. The varainductor further includes a first ground plane over the substrate, the first ground plane disposed on a first side of the signal line, and a second ground plane over the substrate, the second ground plane disposed on a second side of the signal line opposite the first side of the signal line. The varainductor further includes a first floating plane over the substrate, the first floating plane disposed between the first ground plane and the signal line, and a second floating plane over the substrate, the second floating plane disposed between the second ground plane and the signal line. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the first ground plane to the first floating plane, and to selectively connect the second ground plane to the second floating plane. | 09-18-2014 |
20140292400 | FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting. | 10-02-2014 |
20140333355 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL. | 11-13-2014 |
20140334063 | VERTICAL METAL INSULATOR METAL CAPACITOR - A method of forming a capacitor comprises forming a first electrode of the capacitor over a substrate. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures on the bottom conductive plane. The method also comprises forming an insulating structure over the first electrode. The method further comprises forming a second electrode of the capacitor over the insulating structure. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures under the top conductive plane. The first vertical conductive structures of the plurality of first vertical conductive structures and the second vertical conductive structures of the plurality of second vertical conductive structures are interlaced with each other. | 11-13-2014 |
20150020039 | CASCODE CMOS STRUCTURE - A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage. | 01-15-2015 |