Patent application number | Description | Published |
20080200842 | Apparatus and Method For Measuring in Vivo Biomechanical Properties of Skin - An assembly for measuring in vivo biomechanical properties of skin, comprising a testing device, said testing device comprising; a first pad attachable to the skin a second pad attachable to the skin, at a known distance from the first pad; said attachability of the pads to the skin to prevent relative movement between the respective pad and the skin to which it is attached; a forcing means for applying a force to the first pad, whilst said pads are attached to the skin, along a first axis connecting the first and second pad, to induce a corresponding relative movement between the pads due to deformation of the skin between said pads; a force measurement device for measuring the applied force, and; a displacement measurement device for measuring the corresponding induced movement. | 08-21-2008 |
20110319792 | APPARATUS AND METHOD FOR MEASURING IN VIVO BIOMECHANICAL PROPERTIES OF SKIN - An assembly for measuring in vivo biomechanical properties of skin, comprising a testing device, said testing device comprising; a first pad attachable to the skin a second pad attachable to the skin, at a known distance from the first pad; said attachability of the pads to the skin to prevent relative movement between the respective pad and the skin to which it is attached; a forcing means for applying a force to the first pad, whilst said pads are attached to the skin, along a first axis connecting the first and second pad, to induce a corresponding relative movement between the pads due to deformation of the skin between said pads; a force measurement device for measuring the applied force, and; a displacement measurement device for measuring the corresponding induced movement. | 12-29-2011 |
Patent application number | Description | Published |
20090291311 | METHOD OF FORMING A NANOSTRUCTURE - A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm. | 11-26-2009 |
20100096695 | HIGH STRESS FILM - A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor. | 04-22-2010 |
20100167505 | METHODS FOR REDUCING LOADING EFFECTS DURING FILM FORMATION - A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior. | 07-01-2010 |
20110108928 | METHOD FOR FORMING HIGH-K METAL GATE DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance. | 05-12-2011 |
20110193161 | METHOD AND APPARATUS OF FORMING A GATE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type. | 08-11-2011 |
20110201172 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate. | 08-18-2011 |
20110230042 | METHOD FOR IMPROVING THERMAL STABILITY OF METAL GATE - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer. | 09-22-2011 |
20120012937 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer. | 01-19-2012 |
20120074475 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region. | 03-29-2012 |
20120083095 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY THINNING HARDMASK LAYERS ON FRONTSIDE AND BACKSIDE OF SUBSTRATE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate. | 04-05-2012 |
20130012011 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer. | 01-10-2013 |
20130078809 | SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS - A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture. | 03-28-2013 |
20140045328 | INTERCONNECTION STRUCTURE FOR N/P METAL GATES - A method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS) includes forming an opening in a dielectric layer over a substrate and forming a dummy electrode in a first portion of the opening in the dielectric layer. The method further includes filling a second portion of the opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the opening and removing the dummy electrode. The method further includes depositing a first work-function metal layer in the first and second portions, whereby the first work-function metal layer is over the second work-function metal layer in the opening and depositing a signal metal layer over the first work-function metal layer in the first and second portions. | 02-13-2014 |
Patent application number | Description | Published |
20110248019 | METHOD FOR TREATING HYDROCARBON FLUIDS USING PULSATING ELECTROMAGNETIC WAVE IN COMBINATION WITH INDUCTION HEATING - A method for treating hydrocarbon fluids using pulsating electromagnetic wave in combination with induction heating is provided, which comprise the steps of mounting an induction coil onto a conduit having a central axis from which the hydrocarbon fluid to be treated flows, the induction coil being coaxially disposed with the conduit and having an inner diameter which forms a predetermined gap with an outer periphery of the conduit; subjecting the hydrocarbon fluid through the conduit; and applying a time-varying frequency current to the induction coil to produce pulsating electromagnetic field and induction heating around the induction coil, such that the combined effect of the pulsating electromagnetic field and the induction heating is induced in the fluid to prevent and/or reduce build-up of or natural deposition of paraffin, asphaltene or the like contained in the fluid and reduce a viscosity of the fluid in production lines, flow transmission lines, pipelines and oil storage. | 10-13-2011 |
20120137882 | Method For Treating Hydrocarbon Fluids Using Pulsting Electromagnetic Wave in Combination With Induction Heating - A method for electrolytically producing alkaline water comprises the steps of (a) providing an electrolytic cell ( | 06-07-2012 |
20120205246 | SYSTEM AND METHOD FOR PREVENTION OF ADHESION OF MARINE ORGANISMS TO A SUBSTRATE CONTACTING WITH SEAWATER - A system and a method for prevention of adhesion of marine organisms to a substrate contacted with seawater are provided. The system comprises a generator ( | 08-16-2012 |
20140255290 | METHOD FOR CARBONIZING CARBON DIOXIDE AND APPLICATION THEREOF - The invention relates to a method for carbonizing carbon dioxide, comprising the step of contacting carbon dioxide with a solution of chelating agent or a solution of substance which exhibits chelating properties under dynamic conditions to generate oxygen and carbon particles. The method of the invention is significantly more economical and convenient and do not cause harm to the environments. The invention also exhibits a novel and unique feature that elemental carbon and oxygen are generated as final products under normal room temperature and atmosphere, and the carbon can be recovered as an energy source. | 09-11-2014 |
20140290482 | COMPOSITE ELECTRODE FOR ELECTROLYTICALLY PRODUCING ALKALINE WATER, APPARATUS COMPRISING THE SAME AND USE OF THE ALKALINE WATER PRODUCED - The present invention provides a permanent and cost-effective composite electrode for electrolytically producing alkaline water, comprising an electrode core made of steel, a filler densely packed around the electrode core, said filler capable of creating a mildly aqueous and alkaline environment to motivate formation of a layer of magnetite over a surface of the electrode core, and a housing enclosing the filler, said housing having a pore size selected such that very low permeation of gas and liquid takes place. The invention also provides an apparatus comprising the composite electrode, and the use of the alkaline water produced by the apparatus of the invention. According to the invention, no additional undesired side products, such as toxic chlorine gas and other pollutants, are produced and discharged to the environment. | 10-02-2014 |
20150183663 | SYSTEM AND METHOD OF BALLAST WATER TREATMENT WITH CONTINUOUS BIOFOULING CONTROL - Embodiments of the invention relate to ballast water treatment system and method onboard ships or sea-going vessels. The system includes a filtration system, a UV disinfection system and a biofouling control system, which is adapted to provide continuous control of multiplication of marine organisms even during an absence of a ballasting and a de-ballasting process. | 07-02-2015 |
20150218712 | SYSTEM AND METHOD FOR PROVIDING CORROSION PROTECTION OF METALLIC STRUCTURE USING TIME VARYING ELECTROMAGNETIC WAVE - The present invention provides a system and a method for providing corrosion protection of a metallic structure using time varying electromagnetic wave. The system comprises: a generator for generating electromagnetic wave having a time varying frequency, said generator having at least two output terminals in electrical connection respectively with first and second excitation sites positioned in a spaced manner on the metallic structure, allowing for subjecting the metallic structure to the electromagnetic wave; and an electric power source connected to the generator for applying a driving voltage to the generator to drive the generation of the electromagnetic wave; wherein the driving voltage and/or the frequency of the electromagnetic wave are selected such that the metallic structure is energized to form in-situ a passive oxidized species of the metal on a surface of the metallic structure, which species is insusceptible to corrosion. | 08-06-2015 |
20150232352 | SYSTEM AND METHOD FOR PREVENTION OF ADHESION OF ORGANISMS IN WATER TO A SUBSTRATE IN CONTACT WITH WATER - The present invention provides a system for prevention of adhesion of organisms in water to a substrate in contact with the water, wherein the substrate and the water flowing around the substrate form together a treated region, comprising a generator for producing electromagnetic wave having a time varying frequency, in electrical connection with a first excitation site of the treated region and with an avalanche current suppressor having its another terminal connected with a second excitation site of the treated region. A selected voltage is applied to the generator such that the generator is triggered to produce the electromagnetic wave capable of inducing an avalanche current to shock or kill the organisms. The invention also provides a method for prevention of adhesion of organisms in water to a substrate in contact with the water. | 08-20-2015 |
Patent application number | Description | Published |
20110267789 | ETCH-BACK TYPE SEMICONDUCTOR PACKAGE, SUBSTRATE AND MANUFACTURING METHOD THEREOF - A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad. | 11-03-2011 |
20120058604 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE CARRIER AND MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE USING THE SAME - A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed. | 03-08-2012 |
20120153466 | PACKAGE STRUCTURE - A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively. | 06-21-2012 |
20120220118 | CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature. | 08-30-2012 |
20130113099 | PACKAGE CARRIER, PACKAGE CARRIER MANUFACTURING METHOD, PACKAGE STRUCTURE FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer. | 05-09-2013 |
20130161809 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SUBSTRATE STRUCTURE - A substrate structure, a semiconductor package device and a manufacturing method of substrate structure are provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. | 06-27-2013 |
20130175707 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE - A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure. | 07-11-2013 |
20140167240 | SEMICONDUCTOR DEVICE CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer. | 06-19-2014 |
20140299984 | CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature. | 10-09-2014 |
20150111345 | ETCH-BACK TYPE SEMICONDUCTOR PACKAGE, SUBSTRATE AND MANUFACTURING METHOD THEREOF - A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad. | 04-23-2015 |
Patent application number | Description | Published |
20090167466 | TUNABLE HIGH QUALITY FACTOR INDUCTOR - An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor. | 07-02-2009 |
20100295153 | INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor. | 11-25-2010 |
20120007214 | INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor. | 01-12-2012 |
20120274434 | INTEGRATED TRANSFORMER - A device having a substrate and a dielectric layer disposed over the substrate is disclosed. The device includes a transformer layout disposed in the dielectric layer. The transformer layout includes an integrated transformer having primary and secondary coil elements. The first and second coil elements are configured to result in noise-self cancellation effect. | 11-01-2012 |
Patent application number | Description | Published |
20090251541 | Intelligent Vehicle Access Control System - An apparatus for the automatic inspection of a motor vehicle has an identification and psychological profiling zone, an automatic inspection zone and a manual inspection zone. A biometric and heart rate detection station and an attached console are located in zone one. Undercarriage scanning equipment and an explosives detection portal are located in zone two. The apparatus also has one or more fixed cameras, an alarm or other alerting mechanisms and a physical barrier. A vehicle detection mechanism detects the entry of a vehicle into zone two and captures an image of the vehicle number plate. When the captured biometric data and number plate data indicate that the driver is authorized to drive the particular vehicle into the secured zone, and if no abnormalities or foreign objects in the undercarriage image are detected, the driver is allowed to proceed. | 10-08-2009 |
20110063445 | RUNWAY SURVEILLANCE SYSTEM AND METHOD - A surveillance system and method for detecting a foreign object, debris, or damage (FOD) on a runway. The system comprises one or more cameras for capturing images of the runway; and an image processing system for detecting the FOD on the runway based on adaptive image processing of the images captured by the cameras; wherein the surveillance system is adaptively operable for FOD detection under both day and night ambient light conditions without assisted illumination such as infrared or laser illuminators. | 03-17-2011 |
20130329052 | SURVEILLANCE SYSTEM AND A METHOD FOR DETECTING A FOREIGN OBJECT, DEBRIS, OR DAMAGE IN AN AIRFIELD - A surveillance system and method for detecting a foreign object, debris, or damage in an airfield, the surveillance system comprising: one or more cameras for capturing images of the airfield; a processing unit for detecting the foreign object, debris or damage in the airfield from the images captured by the one or more cameras; and a weapons impact surveillance system for detecting weapon impact in the airfield and directing the one or more cameras to capture images in an area of the detected weapon impact. | 12-12-2013 |
Patent application number | Description | Published |
20080284552 | INTEGRATED TRANSFORMER AND METHOD OF FABRICATION THEREOF - An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction. | 11-20-2008 |
20080284553 | TRANSFORMER WITH EFFECTIVE HIGH TURN RATIO - Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5 p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes. | 11-20-2008 |
20100120244 | INTEGRATED CIRCUIT SHIELD STRUCTURE AND METHOD OF FABRICATION THEREOF - A method of forming an integrated circuit is disclosed. The method includes providing a substrate and forming on the substrate a shield structure comprising a shield member and a ground strap. The shield member comprises a non-metallic portion, and the ground strap comprises a metallic portion. | 05-13-2010 |
Patent application number | Description | Published |
20090201652 | CIRCUIT WITH AN INTEGRATED SHIELD AND HEARING AID - A flexible printed circuit board having an integrated shield, a circuit based thereon, and a hearing aid having the circuit, are provided. The flexible printed circuit board includes a mount layer, a metallization layer and a shielding layer for shielding against electromagnetic interference influences. It can be bent about a respective bending axis in at least two different bending areas, in which the two bending axes are at an angle of at least 45 degrees to one another. The shielding layer extends at least over the two bending areas. A circuit based on the printed circuit board can be fitted with electronic components in at least one circuit area and can be bent in the bending areas in such a way that the circuit area is shielded by the shielding layer against electromagnetic interference influences in at least three spatial directions which are substantially at right angles to one another. | 08-13-2009 |
20090257608 | HEARING AID WITH A DROP SAFEGUARD - A hearing aid with a drop safeguard has an accelerometer, an electrical circuit, and a memory. The accelerometer generates an electrical signal in dependence on an acceleration of the hearing aid. The signal is transmitted to the electrical circuit which uses this to determine a jerky acceleration of the hearing aid. The electrical circuit saves the respectively current settings of the hearing aid to the memory in the case of a jerky acceleration of the hearing aid. After the hearing aid is dropped, the settings can be reconstructed from the memory so that as a result this prevents the settings of the hearing aid from being changed. | 10-15-2009 |
20100054514 | Electrical Circuit, Electrical Small Appliance, in Particular a Hearing Aid, Having the Electrical Circuit, and Use of the Electrical Circuit for Producing the Electrical Small Appliance - An electrical circuit has a printed circuit board which is lengthened at the side in the form of at least one longitudinal contact projection having at least one electrical conductor track and a solder point disposed at the end of the conductor track. Because of its mechanical flexibility, the contact projection allows flexible contact to be made with other electronic components, with little effort. An electrical circuit such as this is particularly highly suitable for electrical small appliances, in particular for a hearing aid. | 03-04-2010 |
20100098279 | Hearing apparatus comprising a membrane on the battery compartment interior - A hearing apparatus with a housing including a housing interior is provided. Signal processing components are accommodated in the housing interior. The hearing apparatus includes a battery compartment fastened in or on the housing, which has a battery compartment interior into which a battery is inserted for supplying power to the hearing apparatus. Further, a membrane is provided, which separates the housing interior from the battery compartment interior. The membrane is fastened to the housing or to the battery compartment. | 04-22-2010 |
20100202646 | HEARING DEVICE WITH SUPPORTING HOOK RECOGNITION - The fitting of hearing aids and other hearing devices is intended to be made more comfortable. For this, provision is made for a hearing device with a housing which contains a signal processing unit and has a sound outlet. A supporting hook for attaching the hearing device to an ear or a head can be fixed on the sound outlet of the housing such that sound emanating from the sound outlet is guided through the supporting hook. A sensor for detecting the type of supporting hook is arranged in or on the housing. The sensor controls the signal processing unit as a function of the detected type of supporting hook. Thus, the user can for example use different types of supporting hooks without having to decide on a type of supporting hook during the first fitting. Moreover, the degree of mass production of the hearing aid can be further increased by the automatic recognition of the type of supporting hook. | 08-12-2010 |