Patent application number | Description | Published |
20080224278 | CIRCUIT COMPONENT AND METHOD OF MANUFACTURE - An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured. | 09-18-2008 |
20110115061 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE HAVING A TRENCH - An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate. | 05-19-2011 |
20120306066 | ELECTRONIC DEVICE INCLUDING A PACKAGING SUBSTRATE HAVING A TRENCH - An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate. | 12-06-2012 |
20150189772 | SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package. | 07-02-2015 |
20150364847 | FLEXIBLE PRESS FIT PINS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS - A pin for a semiconductor package includes an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver. A lower portion of the pin is configured to flex to allow an upper portion of the pin to move towards an upper contact surface of a horizontal base of the pin in response to a pressure applied along a direction collinear with a longest length of the pin towards the upper contact surface of the horizontal base when the pin is inserted into a pin receiver. Some implementations of pins include a vertical stop to stop movement of the pin when a surface of the vertical stop contacts the upper contact surface of the horizontal base. Varying implementations of pins include: two curved legs and one vertical stop; two partially curved legs and no vertical stop, and; a single leg bent into an N-shape. | 12-17-2015 |
Patent application number | Description | Published |
20080230684 | Gain Control System for Visible Light Communication Systems - An optical receiver having a photodetector, a variable gain amplifier, and a gain control circuit is disclosed. The photodetector generates a photodetector output signal related to an intensity of light received by the photodetector, the photodetector output signal being characterized by a peak-to-peak signal value. The variable gain amplifier amplifies the photodetector output signal to generate a receiver output signal that is coupled to an external device, the variable gain amplifier having a gain that is determined by a gain control signal. The gain control circuit receives the receiver output signal and generates the gain control signal therefrom. The gain control signal causes the gain of the variable gain amplifier to decrease as a function of the peak-to-peak signal value to reduce changes in the output signal amplitude as a function of the input light signal amplitude. | 09-25-2008 |
20080237453 | COLOR SENSOR WITH INFRARED CORRECTION HAVING A FILTER LAYER BLOCKING A PORTION OF LIGHT OF VISIBLE SPECTRUM(AS AMNENDED) - A light sensor that generates a first output signal indicative of an intensity of light received from a predetermined direction in a first band of wavelengths is disclosed. The light sensor includes a substrate having first and second photodetectors, a first filter layer, and a controller. The photodetectors are sensitive to light in the infrared portion of the optical spectrum as well as to light in the first band of wavelengths, and generate first and second photodetector signals. The first filter layer transmits light in the first band of wavelengths and light in the infrared portion of the optical spectrum while blocking light in a portion of the visible spectrum outside of the first band of wavelengths, without altering light received by the first photodetector. The controller processes the first and second photodetector signals to produce the first output signal that is corrected for infrared in the input light. | 10-02-2008 |
20100302532 | PHOTODETECTOR HAVING DARK CURRENT CORRECTION - A method for determining the light intensity of a light signal in each of a plurality of spectral bands is disclosed and a method for fabricating a photodetector is also disclosed. | 12-02-2010 |
20120006976 | High Resolution, High Speed, Miniaturized Optical Encoder - Disclosed are various embodiments of a single track reflective optical encoder featuring current amplifiers disposed in the signal generating circuit thereof. Voltage amplifiers and their associated feedback resistors are eliminated in the various embodiments disclosed herein, resulting in decreased die size and improved encoder signal accuracy and performance, especially at high speeds The single track optical encoder configurations disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed. | 01-12-2012 |
20120104236 | Hysteresis-Compensating Interpolation Circuits in Optical Encoders - Disclosed are various embodiments of circuitry and methods to compensate for variations in hysteresis associated with the comparators of an interpolation circuit in a single track optical encoder. Such variations in hysteresis may be minimized or eliminated by providing appropriately configured resistor ladder circuits to condition the inputs to the comparators, or by programming or trimming resistors in positive feedback loops of the comparators. The single track optical encoder configurations disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed. | 05-03-2012 |
Patent application number | Description | Published |
20080315388 | VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE - In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed. | 12-25-2008 |
20120237125 | Isolating Background and Foreground Objects in Video - In accordance with some embodiments, background subtraction can be performed by iteratively computing a new expected background image from an old background image using a plurality of consecutive frames. The new expected background image may be computed to be closer to a current frame's pixel value. In some embodiments, a new expected background image may be based on user supplied values so that a user may determine how fast a background image changes. | 09-20-2012 |
20130275639 | METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS - Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device. | 10-17-2013 |
20140006668 | Performing Emulated Message Signaled Interrupt Handling | 01-02-2014 |
20140009378 | User Profile Based Gesture Recognition - An embodiment includes a system recognizing a first user via a camera, selecting a profile for the first user, and interpreting the first user's gestures according to that profile. For example, the embodiment identifies a first user, loads his gesture signature profile, and then interprets the first user forming his fist with his thumb projecting upwards as acceptance of a condition presented to the user (e.g., whether the user wishes to turn a tuner to a certain channel). The embodiment recognizes a second user, selects a profile for the second user, and interprets the second user's gestures according to that profile. For example, the embodiment identifies the second user, loads her profile, and then interprets the second user forming her fist with her thumb projecting upwards as the user pointing upwards. This moves an area of focus upwards on a graphical user interface. Other embodiments are described herein. | 01-09-2014 |
20140156950 | EMULATED MESSAGE SIGNALED INTERRUPTS IN MULTIPROCESSOR SYSTEMS - A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address. | 06-05-2014 |
20140168708 | COMBINING PRINT JOBS - A method and system for combining print jobs is described herein. The method includes loading a print surface containing a first print job and obtaining a second print job. The first print job and the second print job may be combined into a composite file, wherein the composite file is used to adjust the first print job and the second print job. | 06-19-2014 |
20140189182 | METHOD TO ACCELERATE MESSAGE SIGNALED INTERRUPT PROCESSING - Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a messaged signaled interrupt (MSI) request from a device over a bus, and an execution unit coupled to the interrupt controller to execute an interrupt service routine (ISR) associated with the device, the execution unit to retrieve interrupt data from a predetermined memory location specifically allocated to the device and to service the MSI using the interrupt data, without having to obtain the device interrupt data via an input output (IO) transaction. | 07-03-2014 |
20140192677 | NETWORK ROUTING PROTOCOL POWER SAVING METHOD FOR NETWORK ELEMENTS - Methods and apparatus relating to network routing protocols to support power savings in network elements. A most utilized link path network topology for a computer network is discovered using a routing protocol such as a Spanning Tree, link-state, or distance vector routing protocol. In view of the most utilized link path network topology, links are identified as candidates for power management under which a power state of the link and associated network ports are managed to save power under applicable link conditions, such as low utilization. Link power-state change conditions are detected, and in response a corresponding change to the power state of a link is effected by changing the power-state of the network ports at the ends of the link. Power state changes include putting a link into a reduced power state, taking a link offline, and powering a link back up. | 07-10-2014 |
20140195792 | HIDING BOOT LATENCY FROM SYSTEM USERS - Methods and systems may provide for identifying a proximity condition between a system and a potential user of the system. In addition, one or more boot components of the system can be activated in response to the proximity condition, wherein one or more peripheral devices associated with the system are maintained in an inactive state. In one example, at least one of the one or more peripheral devices is placed in an active state in response to detecting an activation condition of the system. | 07-10-2014 |
20140237144 | METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH INTERRUPT DATA - Methods to emulate a message signaled interrupt (MSI) with interrupt data are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory block allocated to a device, an interrupt controller to receive an emulated messaged signaled interrupt (MSI) signal from the memory decoder in response to a posted write transaction to the predetermined memory block initiated from the device, and an execution unit to execute an interrupt service routine (ISR) associated with the device to service the MSI using interrupt data retrieved from the predetermined memory block, without having to obtain the interrupt data from the device via an input output (IO) transaction. | 08-21-2014 |
20140310721 | REDUCING THE NUMBER OF READ/WRITE OPERATIONS PERFORMED BY A CPU TO DUPLICATE SOURCE DATA TO ENABLE PARALLEL PROCESSING ON THE SOURCE DATA - Methods and apparatuses to reduce the number of read/write operations performed by a CPU may involve duplicating source data to enable parallel processing on the source data. A memory controller may be configured to duplicate data written to a first buffer to one or more duplicate buffers that are allocated to one or more processing threads, respectively. In some implementations, the one or more duplicate buffers are dedicated buffers, and the addresses of the first buffer and the one or more duplicate buffers are stored in a register of memory controller. | 10-16-2014 |
20150189504 | METHOD AND APPARATUS FOR SECURE HIGH-BANDWIDTH AD-HOC NETWORKING - The disclosure generally relates to a method, system and apparatus for establishing a secure ad-hoc network. In one embodiment, the disclosure provides a method for establishing an ad-hoc network by: generating a security key at a first device and communicating the security key to a second device using a first communication channel; selecting a network protocol supported by both the first and the second device; exchanging networking information for establishing a second communication channel using the first communication channel, the second communication channel defining an ad-hoc network; and establishing the second communication channel between the first and the second device using the selected network protocol. | 07-02-2015 |
20150195334 | REMOTE USER INTERFACE FOR SELF-SERVICE COMPUTING DEVICE - Embodiments of computer-implemented methods, systems, apparatuses, and computer-readable media (transitory and non-transitory) are described herein for configuring a self-service computing device to provide, to a remote computing device in direct wireless communication with the self-service computing device, data for the remote computing device to render an instance of a user interface operable by a user of the remote computing device to select a product or service offered by the self-service computing device. Other embodiments may be described and/or claimed. | 07-09-2015 |
20160092877 | SECURE USER AUTHENTICATION INTERFACE TECHNOLOGIES - Technologies for secure user authentication include a computing device with a touch screen display coupled to an electronic paper display, and a security engine isolated from a host processor. To process a payment transaction, the computing device invokes the security engine to generate a random virtual keypad layout that is not accessible by the host processor. The virtual keypad layout includes virtual keypad buttons that may be randomly positioned. The security engine displays the virtual keypad layout on the electronic paper display that overlays the touch screen display. The computing device detects touch input using the touch screen and transmits the touch input to the security engine. The security engine determines keypad input based on the touch input by mapping coordinates of the touch input to virtual buttons of the virtual keypad. The security engine authorizes the transaction based on the keypad input. Other embodiments are described and claimed. | 03-31-2016 |
20160105405 | MULTI-KEY GRAPHIC CRYPTOGRAPHY FOR ENCRYPTING FILE SYSTEM ACCELERATION - Embodiments of methods and systems for encrypting and decrypting with encryption attributes are presented. An encryption attribute contains information to identify one or more segments of a file to be encrypted. An encryption process encrypts those one or more segments to generate a partly encrypted file instead of encrypting the entire file. That is, the file includes some data that are encrypted and some data that are not. In one embodiment, at least three encryption keys are used such that the encryption attribute is encrypted with using a third key. | 04-14-2016 |