Patent application number | Description | Published |
20080217941 | Active material enabled self-presenting devices - A self-presenting device includes, a member in physical communication with a vehicle surface, wherein the member is configured to have a first form and a second form, wherein the first form is configured to store the member and the second form is configured to present the member, and an active material in operable communication with the member, wherein the active material is configured to undergo a change in at least one property upon receipt of an activation signal, wherein the change in at least one property is effective to transition the member from the first form to the second form. | 09-11-2008 |
20080294314 | Obstruction Detection Device for Vehicle Door and Method - An obstruction detection device for a motor vehicle having a door assembly movably connected to a vehicle body is provided. The device controls the vehicle door's opening angle to prevent inadvertent contact with an object foreign to the vehicle, while providing the largest opening for vehicle ingress and egress. The obstruction detection device includes a controller that is operatively connected to at least one sensor configured to actively monitor and transmit signals to the controller indicative of the presence and corresponding proximity of the object relative to the door assembly. An actuator is operatively connected to and controlled by the controller. The actuator is configured to apply a selectively variable force that restricts the movement of the vehicle door assembly with respect to the vehicle body when the door is a predetermined distance from the object. | 11-27-2008 |
20090008973 | ACTIVE MATERIAL ACTUATED HEADREST ASSEMBLIES - Active material actuated headrest assemblies and their methods of operation are described herein. The headrests include an active material incorporated in a frame member, a bag, gear device, or the like, wherein the active material actuates upon receipt of an activation signal. | 01-08-2009 |
20090058132 | Active material based concealment assemblies - A concealment assembly includes a component, a member configured to have a first form and a second form, wherein the first form is configured to conceal the component and the second form is configured to expose the component, thereby making the component accessible for use, appearance, or function, and an active material in operable communication with the member, wherein the active material is configured to undergo a change in at least one property upon receipt of an activation signal, wherein the change in at least one property is effective to transition the member from the first form to the second form. | 03-05-2009 |
20110121607 | METHOD OF USING AN ACTIVE MATERIAL BASED CONCEALMENT ASSEMBLY - A method of concealing a component is disclosed. The method includes positioning a member in operable communication with the component, wherein the member is configured to have a first form and a second form, wherein the first form is configured to conceal the component and the second form is configured to expose the component. The method also includes activating an active material in operative communication with the member, wherein the active material is configured to undergo a change in at least one property upon receipt of an activation signal, wherein the change in a property is effective to transition the member from the first form to the second form. | 05-26-2011 |
Patent application number | Description | Published |
20090187904 | Redirection Table for Virtual Machine Guest - In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the processor has intercepted, wherein the guest is executed under control of a virtual machine monitor (VMM), and wherein the redirect unit is configured to redirect instruction fetching by the processor to a routine identified in the IP redirect table instead of exiting to the VMM in response to the intercept of the guest instruction. | 07-23-2009 |
20120144119 | PROGRAMMABLE ATOMIC MEMORY USING STORED ATOMIC PROCEDURES - A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line. | 06-07-2012 |
20120291040 | AUTOMATIC LOAD BALANCING FOR HETEROGENEOUS CORES - A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit. | 11-15-2012 |
20120297163 | AUTOMATIC KERNEL MIGRATION FOR HETEROGENEOUS CORES - A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core. | 11-22-2012 |
20140047079 | SYSTEM AND METHOD FOR EMULATING A DESIRED NETWORK CONFIGURATION IN A CLOUD COMPUTING SYSTEM - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting a cluster of nodes for the computing system from a plurality of available nodes coupled to a communication network based on a comparison of a communication network configuration of an emulated node cluster and an actual communication network configuration of the plurality of available nodes. The method further includes modifying a network configuration of at least one node of a cluster of nodes to modify network performance of the at least one node on a communication network coupled to the cluster of nodes. | 02-13-2014 |
20140047084 | SYSTEM AND METHOD FOR MODIFYING A HARDWARE CONFIGURATION OF A CLOUD COMPUTING SYSTEM - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes determining, based on a shared execution of a workload by a cluster of nodes of the computing system, that at least one node of the cluster of nodes operated at less than a threshold operating capacity during the shared execution of the workload. The method further includes selecting a modified hardware configuration of the cluster of nodes based on the determining such that the cluster of nodes with the modified hardware configuration has at least one of a reduced computing capacity and a reduced storage capacity. | 02-13-2014 |
20140047227 | SYSTEM AND METHOD FOR CONFIGURING BOOT-TIME PARAMETERS OF NODES OF A CLOUD COMPUTING SYSTEM - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes with the selected boot-time configuration to modify at least one boot-time parameter of the at least one node. | 02-13-2014 |
20140047272 | SYSTEM AND METHOD FOR CONFIGURING A CLOUD COMPUTING SYSTEM WITH A SYNTHETIC TEST WORKLOAD - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload. | 02-13-2014 |
20140047341 | SYSTEM AND METHOD FOR CONFIGURING CLOUD COMPUTING SYSTEMS - The present disclosure relates to a method, system, and apparatus for configuring a computing system, such as a cloud computing system. A method includes, based on user selections received via a user interface, configuring a cluster of nodes by selecting the cluster of nodes from a plurality of available nodes, selecting a workload container module from a plurality of available workload container modules for operation on each node of the selected cluster of nodes, and selecting a workload for execution with the workload container on the cluster of nodes. Each node of the cluster of nodes includes at least one processing device and memory, and the cluster of nodes is operative to share processing of a workload. | 02-13-2014 |
20140047342 | SYSTEM AND METHOD FOR ALLOCATING A CLUSTER OF NODES FOR A CLOUD COMPUTING SYSTEM BASED ON HARDWARE CHARACTERISTICS - The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes initiating a hardware performance assessment test on a group of available nodes to obtain actual hardware performance characteristics of the group of available nodes. The method further includes selecting a subset of nodes for the computing system from the group of available nodes based on a comparison of the actual hardware performance characteristics of the group of available nodes and desired hardware performance characteristics. | 02-13-2014 |
Patent application number | Description | Published |
20090157359 | MECHANISM FOR PROFILING PROGRAM SOFTWARE RUNNING ON A PROCESSOR - A processor having one or more processor cores includes execution logic that may execute instructions including one or more processes. Each process may include one or more execution threads. The processor also includes a profiling mechanism that includes monitor logic and a monitor process. The monitor logic may monitor the one or more processes and provide access to performance data associated with the one or more processes without interrupting a flow of control of the one or more processes being monitored. The monitor process may gather the performance data. In addition, the monitor process may include program instructions executable by the one more processor cores while operating in user mode. | 06-18-2009 |
20110055805 | Lightweight Service Based Dynamic Binary Rewriter Framework - A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code. | 03-03-2011 |
20130346531 | SYSTEMS AND METHODS FOR INPUT/OUTPUT VIRTUALIZATION - Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC. | 12-26-2013 |
20140056141 | PROCESSING SYSTEM USING VIRTUAL NETWORK INTERFACE CONTROLLER ADDRESSING AS FLOW CONTROL METADATA - In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow. | 02-27-2014 |
20140059160 | SYSTEMS AND METHODS FOR SHARING DEVICES IN A VIRTUALIZATION ENVIRONMENT - Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions. | 02-27-2014 |
20140068088 | SYSTEMS AND METHODS FOR PROCESSING MEDIA ACCESS CONTROL (MAC) ADDRESSES - Described are a system and method for processing a media access control (MAC) address. A communication is established between a processing device and a network port of a data switching device. The data switching device assigns a MAC address to the processing device. The assigned MAC address is directly associated with the network port of the data switching device absent a learning mechanism. | 03-06-2014 |
20140258688 | BENCHMARK GENERATION USING INSTRUCTION EXECUTION INFORMATION - Methods and systems are provided for generating a benchmark representative of a reference process. One method involves obtaining execution information for a subset of the plurality of instructions of the reference process from a pipeline of a processing module during execution of those instructions by the processing module, determining performance characteristics quantifying the execution behavior of the reference process based on the execution information, and generating the benchmark process that mimics the quantified execution behavior of the reference process based on the performance characteristics. | 09-11-2014 |
20140372734 | User-Level Hardware Branch Records - A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction. | 12-18-2014 |
20150106574 | Performing Processing Operations for Memory Circuits using a Hierarchical Arrangement of Processing Circuits - The described embodiments include a computing device that comprises at least one memory die having memory circuits and memory die processing circuits, and a logic die coupled to the at least one memory die, the logic die having logic die processing circuits. In the described embodiments, the memory die processing circuits are configured to perform memory die processing operations on data retrieved from or destined for the memory circuits and the logic die processing circuits are configured to perform logic die processing operations on data retrieved from or destined for the memory circuits. | 04-16-2015 |
Patent application number | Description | Published |
20090085768 | GLUCOSE SENSOR TRANSCEIVER - The present invention relates to a telemetered characteristic sensor transceiver for exchanging data with at least one remote device. The transceiver includes a housing detachably coupled to a sensor located on a body of a user, the sensor producing a signal indicative of a user characteristic. A processor is formed within the housing and in communication with the sensor for processing the signal produced by the sensor. A transmitter is coupled to the processor for transmitting data to at least one remote device while a receiver is coupled to the processor for receiving data from the at least one remote device. A memory is coupled to the processor for storing data, wherein the processor performs calculations using at least one of the signal produced by the sensor, the data received from the at least one remote device and the data stored in the memory, and performs at least one of storing the calculations in the memory and transmitting the calculations to the at least one remote device through the transmitter. | 04-02-2009 |
20100191086 | SENSING SYSTEM WITH AUXILIARY DISPLAY - A system is provided for sensing blood glucose data of a patient. The system includes a sensor, user interface, and an optional auxiliary device. If the connection between the sensor and user interface is by a wire, the sensor remains powered when the wire is disconnected. The communication between the sensor and the user interface may be wireless. The auxiliary device can be a patient monitor or other display or signal device, which displays information about the blood glucose data collected by the sensor. The sensor is connected to sensor electronics, which include a sensor power supply, a voltage regulator, and optionally a memory and processor. | 07-29-2010 |
20100191087 | SENSING SYSTEM WITH AUXILIARY DISPLAY - A system is provided for sensing blood glucose data of a patient. The system includes a sensor, user interface, and an optional auxiliary device. If the connection between the sensor and user interface is by a wire, the sensor remains powered when the wire is disconnected. The communication between the sensor and the user interface may be wireless. The auxiliary device can be a patient monitor or other display or signal device, which displays information about the blood glucose data collected by the sensor. The sensor is connected to sensor electronics, which include a sensor power supply, a voltage regulator, and optionally a memory and processor. | 07-29-2010 |
20110178381 | SENSING APPARATUS AND PROCESS - A sensing apparatus with a connector, a sensor lead and a sensor module with a spacer placed over electrodes that have been deposited on a substrate. The spacer may have a space for receiving an enzyme. End portions of the sensor module may be encapsulated, such as with molded beads. A sensor lead may attach to the sensor module and may have an outer tubing that passes over the module and attaches to the beads at the end of the sensor module. The sensor lead may also attach to the connector such that the sensing apparatus may be electrically coupled to a pump, electronics or other devices. The sensing apparatus may be implanted into a vein or artery. | 07-21-2011 |
20110203923 | SENSING APPARATUS AND PROCESS - A sensing apparatus with a connector, a sensor lead and a sensor module with a spacer placed over electrodes that have been deposited on a substrate. The spacer may have a space for receiving an enzyme. End portions of the sensor module may be encapsulated, such as with molded beads. A sensor lead may attach to the sensor module and may have an outer tubing that passes over the module and attaches to the beads at the end of the sensor module. The sensor lead may also attach to the connector such that the sensing apparatus may be electrically coupled to a pump, electronics or other devices. The sensing apparatus may be implanted into a vein or artery. | 08-25-2011 |