Patent application number | Description | Published |
20090161413 | MRAM Device with Shared Source Line - In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell. | 06-25-2009 |
20090174453 | System and Method of Conditional Control of Latch Circuit Devices - A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal. | 07-09-2009 |
20090231937 | Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time. | 09-17-2009 |
20100046276 | Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells - A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up. | 02-25-2010 |
20100061144 | Memory Device for Resistance-Based Memory Applications - In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit. | 03-11-2010 |
20100142303 | Digitally-Controllable Delay for Sense Amplifier - Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit. | 06-10-2010 |
20100172173 | System And Method To Read And Write Data A Magnetic Tunnel Junction Element - A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element. | 07-08-2010 |
20100226191 | Leakage Reduction in Memory Devices - A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current. | 09-09-2010 |
20110051537 | Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time. | 03-03-2011 |
20110084685 | Power Saving for Hot Plug Detect - Power saving for hot plug detect (HPD) is disclosed. In a particular embodiment, a method includes detecting, at a source device that is connectable to a sink device, a connection of the source device to the sink device via a connector. The source device includes a DC voltage source and the connection is detected without consuming power from the DC voltage source. | 04-14-2011 |
20130030767 | HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK - System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock. | 01-31-2013 |
20130033329 | System and Method of Controlling Gain of an Oscillator - A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process. | 02-07-2013 |
20130082744 | Apparatus to Implement Symmetric Single-Ended Termination in Differential Voltage-Mode Drivers - A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry. | 04-04-2013 |
20130120040 | SYSTEM AND METHOD OF STABILIZING CHARGE PUMP NODE VOLTAGE LEVELS - A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second circuit coupled to a second drain node of a second supply of the charge pump. The method further includes stabilizing a first voltage of the first drain node and a second voltage of the second drain node responsive to the tuning voltage. | 05-16-2013 |
20130120071 | TUNING VOLTAGE RANGE EXTENSION CIRCUIT AND METHOD - A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor. | 05-16-2013 |
20140101507 | HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK - System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock. | 04-10-2014 |
20140149756 | POWER SAVING DURING A CONNECTION DETECTION - In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal. | 05-29-2014 |