| Patent application number | Description | Published |
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| 20100190345 | Selective Etch-Back Process for Semiconductor Devices - A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH | 07-29-2010 |
| 20100213431 | Treated Chalcogenide Layer for Semiconductor Devices - A phase change memory and a method of manufacture are provided. The phase change memory includes a layer of phase change material treated to increase the hydrophobic nature of the phase change material. The hydrophobic nature of the phase change material improves adhesion between the phase change material and an overlying mask layer. The phase change material may be treated, for example, with a plasma comprising N | 08-26-2010 |
| 20100230757 | Hybrid STI Gap-Filling Approach - A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate. | 09-16-2010 |
| 20100252794 | COMPOSITE FILM FOR PHASE CHANGE MEMORY DEVICES - A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer. | 10-07-2010 |
| 20100270604 | Non-Volatile Memories and Methods of Fabrication Thereof - Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode. | 10-28-2010 |
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| 20090127648 | Hybrid Gap-fill Approach for STI Formation - A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process. | 05-21-2009 |
| 20090209083 | Hybrid Gap-fill Approach for STI Formation - A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material. | 08-20-2009 |
| 20100015776 | Shallow Trench Isolation Corner Rounding - A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration. | 01-21-2010 |
| 20100022084 | Method for Forming Interconnect Structures - Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer. | 01-28-2010 |
| 20100136791 | Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer. | 06-03-2010 |
