Patent application number | Description | Published |
20080209293 | PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES - A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing. | 08-28-2008 |
20090119537 | METHOD FOR REPAIRING MEMORY AND SYSTEM THEREOF - A method for repairing a main memory comprises the steps of: utilizing a spare memory to repair a main memory, wherein the spare memory includes a plurality of spare memory units; allocating a spare memory unit; determining whether available permutations of the allocated spare memory unit cover a newly found defect in the main memory; removing permutations of the spare memory unit failing to cover newly found defects in the main memory; and allocating another spare memory unit to repair the newly found defects if available permutations of the allocated spare memory unit fails to cover the newly found defects. | 05-07-2009 |
20100332177 | TEST ACCESS CONTROL APPARATUS AND METHOD THEREOF - A test access control apparatus includes test access mechanism (TAM) buses and an extended IEEE 1149.1 Test Access Port (TAP) Controller. The TAM buses support memory built-in-self-test (BIST) circuit for the memory known-good-die (KGD) test, scan chains for the logic KGD test; and through-silicon-via (TSV) chains that are configured to conduct the TSV test that verifies any defect in vertical interconnects between any two chip layers of the stacked chip device. The TAP Controller is coupled to the TAM buses and is configured to control the memory KGD test, the logic KGD test and the TSV test between two chip layers. A cost-effective connection or configuration of test access control apparatus in 3D-IC is also present. In accordance with an embodiment of the present invention, a test access control method includes a yield-concerned test methodology for 3D-IC, and an integrated flow of test access control apparatus supporting heterogeneous test protocols of SOC | 12-30-2010 |
20110080184 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
20110080185 | METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF - The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty. | 04-07-2011 |
Patent application number | Description | Published |
20090161431 | BUILT-IN SELF-REPAIR METHOD FOR NAND FLASH MEMORY AND SYSTEM THEREOF - A built-in self-test system applied to NAND flash memory comprises a built-in self-test circuit, a built-in redundancy-analysis circuit, a content addressable memory, a spare memory, a page-mode processor and an address generator. The built-in self-test circuit is configured to test for defective data in a NAND flash memory. The built-in redundancy-analysis circuit is connected to the built-in self-test circuit. The content addressable memory is connected to the built-in redundancy-analysis circuit for storing the address of the defective data. The spare memory is electrically connected to the content addressable memory. The page-mode processor is configured to generate a page address signal and a compensation signal according to an address signal of the NAND flash memory. The address generator is configured to generate a current address signal according to the page address signal and compensation signal to the content addressable memory. | 06-25-2009 |
20090201039 | PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICE - A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system comprising a test head having a first transceiving module; a test station having a test unit couple to the test head to perform test operation; a communication module having a second transceiving module configured to exchange data with the first transceiving module; an integrated circuit device having at least one core circuit being tested; and at least one test module having a self-test circuit couple to the core circuit and the communication module for performing the core circuit self-testing. | 08-13-2009 |
20090245505 | MULTIPLICATION CIRCUIT AND DE/ENCRYPTION CIRCUIT UTILIZING THE SAME - A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator. | 10-01-2009 |
20100281341 | NON-VOLATILE MEMORY MANAGEMENT METHOD - A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased. | 11-04-2010 |
20140062586 | DOUBLE THROUGH SILICON VIA STRUCTURE - This invention discloses a double Through Silicon Via (TSV) structure, including a first die unit, a first signal path, a second signal path, a receiving unit and a second die unit. The first and the second signal paths respectively include a driving unit and a TSV unit. Each driving unit includes a first end, a second end and a third end. The invention divides the signal paths of the conventional double TSV into two different signal paths by two driving units and the receiving unit having OR gate or NOR gate, to avoid generating the problem of signal degradation from the TSV unit with short defect. The invention further disposes a first switch unit, a second switch unit, a first exchange unit, a second exchange unit, a first VDD keeper and a second VDD keeper, to avoid generating the problems of open defect and leakage current. | 03-06-2014 |
20140157076 | DATA ERROR-DETECTION SYSTEM AND METHOD THEREOF - The present invention discloses a data error-detection system and the method thereof. The system includes an initializing module, an encoding module, a decoding module and a restoring module. The initializing module arranges the transmitting data in a 3D matrix to produce information data. The encoding module encodes the information data to produce checking data, and outputs encoding data which includes information data and checking data. The decoding module receives encoding data and detects information data according to the checking data to correct the information data and then produces 3D matrix receiving data. The restoring module produces receiving data according to the 3D matrix receiving data. Herewith, the effect of error-detection and correction of the data can be achieved. | 06-05-2014 |