Patent application number | Description | Published |
20090054475 | HETEROCYCLIC RECEPTOR AGONISTS FOR THE TREATMENT OF DIABETES AND METABOLIC DISORDERS - Compounds and methods are provided for the treatment of, inter alia, Type II diabetes and other diseases associated with poor glycemic control. The compounds of the invention are orally active. | 02-26-2009 |
20090093650 | RESOLUTION OF ALPHA-(PHENOXY)PHENYLACETIC ACID DERIVATIVES WITH NAPHTHYL-ALKYLAMINES - The present invention provides a methods and compounds for producing an enantiomerically enriched α-(phenoxy)phenylacetic acid compound of the formula: | 04-09-2009 |
20100087465 | HETEROCYCLIC RECEPTOR AGONISTS FOR THE TREATMENT OF DIABETES AND METABOLIC DISORDERS - Compounds and methods are provided for the treatment of, inter alia, Type II diabetes and other diseases associated with poor glycemic control. The compounds of the invention are orally active. | 04-08-2010 |
20100087468 | MODULATORS OF PPAR AND METHODS OF THEIR PREPARATION - The present invention is directed to certain novel compounds represented by Formula (I) and pharmaceutically acceptable salts, solvates, hydrates and prodrugs thereof. The present invention is also directed to methods of making and using such compounds and pharmaceutical compositions containing such compounds to treat or control a number of diseases mediated by PPAR such as glucose metabolism, lipid metabolism and insulin secretion, specifically Type 2 diabetes, hyperinsulinemia, hyperlipidemia, hyperuricemia, hypercholesteremia, atherosclerosis, one or more risk factors for cardiovascular disease, Syndrome X, hypertriglyceridemia, hyperglycemia, obesity and eating disorders. | 04-08-2010 |
20100130511 | HETEROCYCLIC RECEPTOR AGONISTS FOR THE TREATMENT OF DIABETES AND METABOLIC DISORDERS - Compounds and methods are provided for the treatment of, inter alia, Type II diabetes and other diseases associated with poor glycemic control. The compounds of the invention are orally active. | 05-27-2010 |
20130281691 | HETEROCYCLIC RECEPTOR AGONISTS FOR THE TREATMENT OF DIABETES AND METABOLIC DISORDERS - Compounds and methods are provided for the treatment of, inter alia, Type II diabetes and other diseases associated with poor glycemic control. The compounds of the invention are orally active. | 10-24-2013 |
20140024830 | HETEROCYCLIC RECEPTOR AGONISTS FOR THE TREATMENT OF DIABETES AND METABOLIC DISORDERS - Compounds and methods are provided for the treatment of, inter alia, Type II diabetes and other diseases associated with poor glycemic control. The compounds of the invention are orally active. | 01-23-2014 |
Patent application number | Description | Published |
20140032947 | TRAINING, POWER-GATING, AND DYNAMIC FREQUENCY CHANGING OF A MEMORY CONTROLLER - A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition. | 01-30-2014 |
20140181391 | HARDWARE CHIP SELECT TRAINING FOR MEMORY USING WRITE LEVELING MECHANISM - A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response. | 06-26-2014 |
20140181392 | HARDWARE CHIP SELECT TRAINING FOR MEMORY USING READ COMMANDS - A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting. | 06-26-2014 |
20140181429 | MULTI-DIMENSIONAL HARDWARE DATA TRAINING BETWEEN MEMORY CONTROLLER AND MEMORY - A method of training a memory interface between a memory controller and a memory module. The method includes programming a delay line of a data strobe with a delay value and programming a reference voltage with a voltage value. The method then writes a data bit pattern to the memory module wherein the data bit pattern is of a first plurality of unique data bit patterns. The data bit pattern is read back and a result is compared with the data bit pattern. A determination is made whether the memory module is in a pass state or an error state based on the comparing. The steps are repeated with another data bit pattern of the first plurality of data bit patterns. The method is repeated for each combination of the data strobe delay value and the reference voltage value. | 06-26-2014 |
20140181451 | HARDWARE COMMAND TRAINING FOR MEMORY USING WRITE LEVELING MECHANISM - A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response. | 06-26-2014 |
20140181452 | HARDWARE COMMAND TRAINING FOR MEMORY USING READ COMMANDS - A method of training command signals for a memory module. The method includes programming a memory controller into a mode wherein a column access strobe is active for a single clock cycle. The method then programs a programmable delay line of the column access strobe with a delay value and performs initialization of the memory module. A read command is then sent to the memory module. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting. | 06-26-2014 |
20140189180 | METHOD AND SYSTEM FOR CHANGING BUS DIRECTION IN MEMORY SYSTEMS - A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level. | 07-03-2014 |
Patent application number | Description | Published |
20080304305 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package. | 12-11-2008 |
20080304306 | HIGH VOLTAGE AND HIGH POWER BOOST CONVETER WITH CO-PACKAGED SCHOTTKY DIODE - A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad. | 12-11-2008 |
20100090755 | Current Limiting Load Switch with Dynamically Generated Tracking Reference Voltage - A current limiting load switch for bridging supply Vss and load with a reference voltage VR | 04-15-2010 |
20100225296 | HIGH VOLTAGE AND HIGH POWER BOOST CONVETER WITH CO-PACKAGED SCHOTTKY DIODE - A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad. | 09-09-2010 |
20110316090 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package on separate electrically isolated die pads. | 12-29-2011 |
20120313613 | HIGH VOLTAGE AND HIGH POWER BOOST CONVETER WITH CO-PACKAGED SCHOTTKY DIODE - A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad. The bottom cathode is electrically connected to the common die pad. It is emphasized that this abstract is being provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-13-2012 |
20130265015 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor. The low voltage controller integrated circuit and the high voltage, vertical, discrete field effect transistor are packaged together in a single package on a common electrically conductive die pad, wherein the controller IC is attached to the die pad using insulating adhesive and the FET is attached to the die pad using conductive adhesive. | 10-10-2013 |
20140253090 | CONFIGURABLE INTEGRATED CIRCUIT ENABLING MULTIPLE SWITCHED MODE OR LINEAR MODE POWER CONTROL TOPOLOGIES - An integrated circuit is operable for implementing any of multiple switched mode or linear power control topologies. The integrated circuit includes a control unit, and functional blocks each of which includes circuitry. The control unit is operable selectively to enable particular ones of the functional blocks in response to an input signal indicative of a particular one of the switched mode or linear mode power control topologies. | 09-11-2014 |