Patent application number | Description | Published |
20090032891 | STRUCTURE OF MAGNETIC RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A structure of magnetic random access memory includes a magnetic memory cell formed on a substrate. An insulating layer covers over the substrate and the magnetic memory cell. A write current line is in the insulating layer and above the magnetic memory cell. A magnetic cladding layer surrounds the periphery of the write current line. The magnetic cladding layer includes a first region surrounding the top of the write current line, and a second region surrounding the side edge of the write current line, and extending towards the magnetic memory cell and exceed by a distance. | 02-05-2009 |
20100109109 | MAGNETIC MEMORY ELEMENT UTILIZING SPIN TRANSFER SWITCHING - A magnetic memory element utilizing spin transfer switching includes a pinned layer, a tunneling barrier layer and a free layer structure. The tunneling barrier layer is disposed on the pinned layer. The free layer structure includes a composite free layer. The composite free layer includes a first free layer, an insert layer and a second free layer. The first free layer is disposed on the tunneling barrier layer and has a first spin polarization factor and a first saturation magnetization. The insert layer is disposed on the first free layer. The second free layer is disposed on the insert layer and has a second spin polarization factor smaller than the first spin polarization factor and a second saturation magnetization smaller than the first saturation magnetization. Magnetization vectors of the first free layer and the second free layer are arranged as parallel-coupled. | 05-06-2010 |
20110001203 | MAGNETIC MEMORY ELEMENT UTILIZING SPIN TRANSFER SWITCHING - A magnetic memory element includes a pinned layer, a tunneling barrier layer, a free layer and a stabilizing layer. The tunneling barrier layer is disposed on the pinned layer. The free layer is disposed on the tunneling barrier layer. The stabilizing layer is disposed on the free layer. | 01-06-2011 |
20110159316 | MAGNETORESISTIVE DEVICE WITH PERPENDICULAR MAGNETIZATION - A magnetoresistive device with perpendicular magnetization includes a magnetic reference layer, a first magnetic multi-layer film, a tunneling barrier layer, a second magnetic multi-layer film, and a magnetic free layer. The magnetic reference layer has a first magnetization direction, perpendicular to the magnetic reference layer. The first magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the magnetic reference layer. The tunneling barrier layer is disposed in contact on the first magnetic multi-layer film. The second magnetic multi-layer film, having non-magnetic material layer, is disposed in contact on the tunneling barrier layer. The magnetic free layer is disposed in contact on the second magnetic multi-layer film, having a second magnetization direction capable of being switched to be parallel or anti-parallel to the first magnetization direction. | 06-30-2011 |
20110241139 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory (MRAM) has a perpendicular magnetization direction. The MRAM includes a first magnetic layer, a second magnetic layer, a first polarization enhancement layer, a second polarization enhancement layer, a barrier layer, a spacer, and a free assisting layer. A pinned layer formed by the first magnetic layer and the first polarization enhancement layer has a first magnetization direction and a first perpendicular magnetic anisotropy. A free layer formed by the second magnetic layer and the second polarization enhancement layer has a second magnetization direction and a second perpendicular magnetic anisotropy. The barrier layer is disposed between the first polarization enhancement layer and the second polarization enhancement layer. The spacer is disposed on the second magnetic layer. The free assisting layer is disposed on the spacer and has an in-plane magnetic anisotropy. The spacer and the barrier layer are on opposite sides of the free layer. | 10-06-2011 |
20120068698 | STRUCTURE OF TMR AND FABRICATION METHOD OF INTEGRATED 3-AXIS MAGNETIC FIELD SENSOR AND SENSING CIRCUIT - A structure of TMR includes two magnetic tunneling junction (MTJ) devices with the same pattern and same magnetic film stack on a same conducting bottom electrode and a parallel connection of conducting top electrode. Each MTJ device includes a pinned layer on the bottom electrode, having a pinned magnetization; a non-magnetic tunneling on the pinned layer; and a free layer on the tunneling layer, having a free magnetization. These two MTJ devices have a collinear of easy-axis and their pinned magnetizations all are parallel to a same pinned direction which has an angle of 45 degree to easy-axis; their free magnetizations initially are parallel to the easy-axis but directions are mutual anti-parallel by applying a current generated ampere field. The magnetic field sensing direction is perpendicular to the easy-axis on the substrate. | 03-22-2012 |
20130161736 | TRENCH METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A trench metal oxide semiconductor transistor device and a manufacturing method thereof are described. The trench metal oxide semiconductor transistor device includes a substrate of a first conductivity type, a drift region of the first conductivity type, a deep trench doped region of a second conductivity type, an epitaxial region of the second conductivity type, a trench gate, a gate insulating layer, a source region, a drain electrode and a source electrode. The drift region has at least one deep trench therein, and the deep trench doped region is disposed in the deep trench. The trench gate passes through the epitaxial region, and a distance between a bottom of the trench gate and a bottom of the deep trench doped region is 0.5˜3 um. | 06-27-2013 |
20140001489 | DOUBLE-RECESSED TRENCH SCHOTTKY BARRIER DEVICE | 01-02-2014 |
20140145207 | Schottky Barrier Diode and Fabricating Method Thereof - A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches. | 05-29-2014 |
20140159053 | SIC TRENCH GATE TRANSISTOR WITH SEGMENTED FIELD SHIELDING REGION AND METHOD OF FABRICATING THE SAME - A SiC trench gate transistor with segmented field shielding region is provided. A drain region of a first conductivity type is located in a substrate. A first drift layer of the first conductivity type is located on the substrate and a second drift layer of the first conductivity type is located on the first drift layer. A base region of a second conductivity type is located on the second drift layer. A gate trench is located between the adjacent base regions. A plurality of segmented field shielding regions of the second conductivity type is placed under a bottom of the gate trench and the space between segmented field shielding regions is the first drift region. A gate dielectric layer is located on a bottom and at a sidewall of the gate trench and a trench gate is formed in the gate trench. | 06-12-2014 |
20140167151 | STEPPED TRENCH MOSFET AND METHOD OF FABRICATING THE SAME - A step trench metal-oxide-semiconductor field-effect transistor comprises a drift layer, a first semiconductor region, a stepped gate and a floating region. The drift layer is of a first conductivity type. The first semiconductor region is of a second conductivity type and located on the drift layer, wherein the drift layer and the first semiconductor region have a stepped gate trench therein. The stepped gate trench at least comprises a first recess located in the first semiconductor region and extending into the drift layer and a second recess located below a bottom of the first recess, wherein a width of the second recess is smaller than a width of the first recess. A floating region is of the second conductivity type and located in the drift layer below the second recess. | 06-19-2014 |
20140175559 | INTEGRATED DEVICE HAVING MOSFET CELL ARRAY EMBEDDED WITH BARRIER SCHOTTKY DIODE - Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells. | 06-26-2014 |
20140176132 | MAGNETIC FIELD SENSORS AND SENSING CIRCUITS - A magnetic sensor for sensing an external magnetic field includes first and second electrodes and first and second magnetic tunneling junctions. The first and second electrodes are disposed over a substrate; and the first and second magnetic tunneling junctions are conductively disposed between the first and second electrodes and connected in parallel between the first and second electrodes. The first and second magnetic tunneling junctions are arranged along a first easy axis of the magnetic sensor. The first magnetic tunneling junction includes a first pinned magnetization and a first free magnetization, and the second magnetic tunneling junction includes a second pinned magnetization and a second free magnetization. The first free magnetization and the second free magnetization are arranged substantially in parallel to the first easy axis and in substantially opposite directions. | 06-26-2014 |