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Cheng-Tung
Cheng-Tung Hsu, Yun-Ling Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080258233 | Semiconductor Device with Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 10-23-2008 |
| 20100330755 | Semiconductor Device With Localized Stressor - A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors. | 12-30-2010 |
Cheng-Tung Hsu, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100125449 | Integratd phonetic Chinese system and inputting method thereof - An Integrated Phonetic Chinese System includes a module of Chinese pronunciation keys, a module of Romanized Chinese scripts, a module of input method that allows users to input Chinese characters and pronunciation keys and Romanized scripts and a module of advanced input method utilizing a 24 key position matrix that allows users to input Chinese characters and pronunciation keys and Romanized script with maximum speed and efficiency. | 05-20-2010 |
| 20100235163 | METHOD AND SYSTEM FOR ENCODING CHINESE WORDS - A Chinese character or word encoding system and method for encoding a Unicode Differentiation Index (UDI) into the least significant 3 bits of one of the three component color of the foreground color of the RTF Chinese text. This encoded UDI value allows the correct identification of the encoded Chinese word. It also allows the identification of the traditional Chinese or simplified Chinese counterpart correctly. Further, the encoded UDI allows the identification of the font file differentiator when user is generating a correct Dualese script for a given Chinese word, wherein Dualese refers to a dual-script-in-one type of script. | 09-16-2010 |
Cheng-Tung Lin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100155849 | TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MC | 06-24-2010 |
Cheng-Tung Lin, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100084718 | ADVANCED METAL GATE METHOD AND DEVICE - The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure. | 04-08-2010 |
Cheng-Tung Lin, Jhudong TW
| Patent application number | Description | Published |
|---|---|---|
| 20080299754 | Methods for forming MOS devices with metal-inserted polysilicon gate stack - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer. | 12-04-2008 |
| 20090085126 | Hybrid metal fully silicided (FUSI) gate - A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer. | 04-02-2009 |
| 20090233410 | Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices - A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation. | 09-17-2009 |
Cheng-Tung Lin, Taichung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110178171 | COMPOUNDS FOR CANCER THERAPY - A method of inhibiting the cellular proliferation of at least one selected from the group consisting of androgen dependent prostate cancer cells, androgen independent prostate cancer cells, oral cancer cells, liver cancer cells (hepatoma), and gastric cancer cells in a subject is provided, wherein the method comprises administrating to the subject an effective amount of an active component selected from the group consisting of Z form isochaihulactone (Z-K8) of the following formula (I), E form isochaihulactone (E-K8) of the following formula (II), a pharmaceutically acceptable salt of Z-K8 or E-K8, a pharmaceutically acceptable ester of Z-K8 or E-K8, and combinations thereof: | 07-21-2011 |