Cheng, NY

Alexander L. Cheng, Scarsdale, NY US

Patent application number	Description	Published
20090059815	Self- organizing multi-channel mesh network - A system for self-organizing and auto-configuring mesh networks is disclosed. Special nodes (deemed special for their topological significance) are used as a starting point for forming clusters of fully connected nodes. Here, all nodes can communicate directly with one another and links are scheduled to meet the traffic requirements as indicated by their individual configuration and topological positions. Links that do not interfere with each other are scheduled to operate concurrently, thereby increasing the bandwidth offered by the whole system. When there is change to the system, such as leaving or introduction of a node, the system will adjust with minimum impact on its operation. Once all of the clusters are formed in a system, the clusters are now capable of inter-cluster communications with an increase in bandwidth for such communications.	03-05-2009

Austin Cheng, Ithaca, NY US

Patent application number	Description	Published
20120091858	PARYLENE-C AS A PIEZOELECTRIC MATERIAL AND METHOD TO MAKE IT - A parylene C polymer that is electrically poled such that it is piezoelectric is presented. Methods for manufacturing the piezoelectric parylene C polymer with an optimal piezoelectric coefficient d33 are also disclosed. Actuators formed with piezoelectric parylene C are disclosed as well as sensor devices that incorporate piezoelectric parylene C using charge integrator circuits in which the integration time is longer than likely adiabatic temperature transients.	04-19-2012

Cheng-Wei Cheng, White Plains, NY US

Patent application number	Description	Published
20120248535	SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET) AND INTEGRATED CIRCUIT (IC) CHIP - Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.	10-04-2012
20120285520	WAFER BONDED SOLAR CELLS AND FABRICATION METHODS - A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.	11-15-2012
20120322244	METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.	12-20-2012
20130048061	MONOLITHIC MULTI-JUNCTION PHOTOVOLTAIC CELL AND METHOD - A device and method for fabrication of a multi-junction photovoltaic device includes providing a parent substrate including a single crystal III-V material. The parent substrate forms a III-V cell of the multi-junction photovoltaic device. A lattice-matched Germanium layer is epitaxially grown on the III-V material to form a final cell of the multi-junction photovoltaic device. The Germanium layer is bonded to a foreign substrate.	02-28-2013
20130071999	HIGH THROUGHPUT EPITAXIAL LIFT OFF FOR FLEXIBLE ELECTRONICS - A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.	03-21-2013
20130082303	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.	04-04-2013
20130082356	HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.	04-04-2013

Chieh-Min Cheng, Webster, NY US

Patent application number	Description	Published
20120244466	Toner wash comprising ionic liquid - A washing process using one or more ionic liquids (ILs) as a washing aid agent for toners, including toners produced using such ILs, such as, low melt toners, is provided. ILs are environmentally sound, green solvents that act to swell toner particle surfaces so that surface absorbed and adsorbed pollutants, such as, surfactants and other manufacturing reactants, can be effectively removed. The resulting toners have good charging, charge maintenance and RH sensitivity.	09-27-2012

Chong Cheng, Williamsville, NY US

Patent application number	Description	Published
20100022741	BRUSH COPOLYMERS - A copolymer of formula 1 in which M	01-28-2010

Chris Cheng, New York, NY US

Patent application number	Description	Published
20090171743	SERVICE REQUEST SYSTEM WITH NATURAL SERVICE PROVIDER PROFILING AND METHODS THEREOF - A system and method for managing service requests performs the steps of loading profile settings for service providers, where the profile settings comprise a two dimensional matrix of actions and objects, processing a work order by determining task involved in the accomplishment of the work order, mapping the profile settings into a hierarchy of determined tasks of the work order and providing a listing of service providers for the work order through results of the mapping step.	07-02-2009

Christopher D. Cheng, Schenectady, NY US

Patent application number	Description	Published
20110133473	SYSTEMS AND METHODS FOR ASSEMBLING A GEARBOX HANDLING ASSEMBLY FOR USE IN A WIND TURBINE - A method of assembling a gearbox handling assembly to facilitate removal of a gearbox from a wind turbine uptower from the wind turbine. The wind turbine includes a rotor rotatably coupled to the gearbox with a rotor shaft. The gearbox and the rotor shaft are supported from a support frame. The method includes coupling a support assembly between the gearbox and the support frame for supporting the gearbox from the support frame. A positioning assembly is coupled to the support frame. The positioning assembly is configured to contact the gearbox to move the gearbox between a first position wherein the gearbox is operatively coupled to the rotor shaft and a second position wherein the gearbox is operatively decoupled and spaced from the rotor shaft to facilitate removing the gearbox from the wind turbine without removing the rotor from the wind turbine.	06-09-2011
20120024053	SYSTEM AND METHOD FOR DETECTING ICE ON A WIND TURBINE ROTOR BLADE - A system and method for detecting ice on a rotor blade of a wind turbine are disclosed. In one embodiment, the method may include pitching the rotor blade across a range of pitch angles, monitoring an ice-related parameter of the wind turbine as the rotor blade is pitched and comparing the monitored ice-related parameter to a predetermined baseline profile for the ice-related parameter.	02-02-2012

Fang-Chen Cheng, Randolf, NY US

Feng Cheng, Chappaqua, NY US

Patent application number	Description	Published
20080215401	METHOD AND APPARATUS FOR OPERATIONAL RISK ASSESSMENT AND MITIGATION - Risk in business management is analyzed based on a probabilistic network approach which quantifies the impact of operational risk on financial metrics such as Value-at-Risk (VAR) and/or Potential Losses (PL). This approach provides further capability to determine the optimal placement of one or more countermeasures within a system to minimize the impact of operational risks.	09-04-2008
20080215410	LARGE INVENTORY-SERVICE OPTIMIZATION IN CONFIGURE-TO-ORDER SYSTEMS - A manufacturing process is migrated from an existing operation to a configure-to-order (CTO) system. As the CTO operation will eliminate the “machine-type model” (MTM) inventory of the existing operation, the emphasis is shifted to the components, or “building blocks”, which will still follow the build-to-stock scheme, due to their long leadtimes, and hence still require inventory. The solution involves an inventory-service trade-off of the new CTO system, resulting in performance gains, in terms of reduced inventory cost and increased service level. Other benefits include better forecast accuracy through parts commonality and risk-pooling, and increased customer demand, as orders will no longer be confined within a restricted set of pre-configured MTMs.	09-04-2008
20090240544	SYSTEM AND METHOD FOR DETERMINING ORDER FULFILLMENT ALTERNATIVE WITH MULTIPLE SUPPLY MODES - A system and method for optimizing order fulfillment by considering multiple supply modes in one aspect, plans supply of inventory by forecasting demand, estimating accuracy of said forecasted demand, and establishing reorder point policy based at least on said accuracy of said forecasted demand and a plurality of supply transportation modes. Current inventory position is monitored and if the current inventory position is below the reorder point policy, orders are placed according to a selected shipping method. The selected shipping method may be based at least on customer order priority and transportation budget.	09-24-2009
20090240545	ADAPTIVE PRODUCT CONFIGURATION MODEL - The adaptive product conditioning is a computer-implemented method for identifying product configurations that can be provided to customers in reaction to supply imbalances. The methodology uses data mining techniques to collect and analyze business level meta data to coordinate supply and sales goals in terms of optimizing profits or managing product and technology transitions.	09-24-2009
20100088136	SYSTEM AND METHOD FOR DETERMINING CARBON EMISSION-CONSCIOUS ORDER FULFILLMENT ALTERNATIVES WITH MULTIPLE SUPPLY MODES - A system and method for optimizing order fulfillment by considering multiple supply modes in one aspect, plans supply of inventory by forecasting demand, estimating accuracy of said forecasted demand, and establishing reorder point policy based at least on said accuracy of said forecasted demand, a plurality of supply transportation modes, cost of carbon emissions and limit on carbon emission credits. Current inventory position is monitored and if the current inventory position is below the reorder point policy, orders are placed according to a selected shipping method. The selected shipping method may be based at least on customer order priority, transportation budget, and carbon emission limit.	04-08-2010
20110178948	METHOD AND SYSTEM FOR BUSINESS PROCESS ORIENTED RISK IDENTIFICATION AND QUALIFICATION - A method and system for identifying and quantifying a risk is disclosed. In one embodiment, the method comprises forming a two-dimensional risk matrix, wherein a first dimension of the matrix comprises risk variable categories and a second dimension comprises standard business processes, placing a risk variable onto the two-dimensional risk matrix, wherein the risk variable is categorized by one of the risk variable categories and one of the standard business processes, connecting the variable node with another risk variable in the two-dimensional risk matrix, and applying a learning method to the two-dimensional risk matrix to compose a risk model to use for quantifying the risk. The system comprises a processor operable to perform the steps embodied by the method.	07-21-2011
20110218890	ADAPTIVE PRODUCT CONFIGURATION MODEL - The adaptive product conditioning is a computer-implemented method for identifying product configurations that can be provided to customers in reaction to supply imbalances. The methodology uses data mining techniques to collect and analyze business level meta data to coordinate supply and sales goals in terms of optimizing profits or managing product and technology transitions.	09-08-2011
20120310793	SYSTEM AND METHOD FOR DETERMINING CARBON EMISSION-CONSCIOUS ORDER FULFILLMENT ALTERNATIVES WITH MULTIPLE SUPPLY MODES - A system and method for optimizing order fulfillment by considering multiple supply modes in one aspect, plans supply of inventory by forecasting demand, estimating accuracy of said forecasted demand, and establishing reorder point policy based at least on said accuracy of said forecasted demand, a plurality of supply transportation modes, cost of carbon emissions and limit on carbon emission credits. Current inventory position is monitored and if the current inventory position is below the reorder point policy, orders are placed according to a selected shipping method. The selected shipping method may be based at least on customer order priority, transportation budget, and carbon emission limit.	12-06-2012

Patent applications by Feng Cheng, Chappaqua, NY US

Gisela C. Cheng, Poughkeepsie, NY US

Patent application number	Description	Published
20110126154	INTELLIGENT COMMAND PREDICTION - A method, system, and computer program product for intelligent command prediction are provided. The method includes determining a command prediction preference associated with a user from user profile data, and selecting one or more command history repositories responsive to the command prediction preference. The one or more command history repositories include command history data collected from a plurality of users and classification data associated with the plurality of users. The method also includes calculating command probabilities for commands in the command history data of the selected one or more command history repositories as a function of the classification data associated with the plurality of users in relation to the user. The method additionally includes presenting a next suggested command as a command from the command history data of the selected one or more command history repositories with a highest calculated command probability.	05-26-2011

Huai-Yu Cheng, White Plains, NY US

Patent application number	Description	Published
20120326111	Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS - A phase change material comprises Ge	12-27-2012

Jin Cheng, Forest Hills, NY US

Patent application number	Description	Published
20120134964	HUMAN MATRIX METALLOPROTEINASE-8 GENE DELIVERY ENHANCES THE ONCOLYTIC ACTIVITY OF A REPLICATING ADENOVIRUS - The present invention discloses a method of treating cancer in a subject. This involves co-administering a replicating virus and a matrix metalloproteinase to the subject under conditions effective to treat cancer. It also relates to a method of enhancing the delivery to and distribution within a tumor mass of therapeutic viruses. This involves co-administering a replicating virus and a matrix metalloproteinase to the tumor mass under conditions effective to enhance the delivery to and distribution within the tumor mass of therapeutic viruses. Another aspect relates to a cancer therapeutic. This involves a replicating virus and a matrix metalloproteinase.	05-31-2012

Jiqi Cheng, Bolden, NY US

Patent application number	Description	Published
20090066727	System for extended high frame rate imaging with limited-diffraction beams - A system for producing a high frame rate image includes transmitting a single weighted spatial frequency signal of energy toward an object to be imaged; weighting multiple receive spatial frequency signals from the object, or by performing a spatial Fourier transform; reconstructing an image data set from the single transmitted spatial frequency signal and the multiple receive spatial frequency signals; and, reconstructing the high frame rate, high resolution and high contrast image from the image data set.	03-12-2009

Joy Cheng, Armonk, NY US

Patent application number	Description	Published
20110294068	Self-Segregating Multilayer Imaging Stack With Built-In Antireflective Properties - A coating process comprises forming a patterned material layer on a substrate using a self-segregating polymeric composition comprising a polymeric photoresistive material and an antireflective coating material contained in a single solution. When depositing this solution on a substrate and removing the solvent, the two materials self-segregate into two layers. This produces a coated substrate having a uniaxial bilayer coating oriented in a direction orthogonal to the substrate with a top photoresistive coating layer and a bottom antireflective coating layer. Pattern-wise exposing the coated substrate to imaging radiation and contacting the coated substrate with a developer, produces the patterned material layer. Any optional top coat material and a portion of the photoresist layer can be simultaneously removed from the coated substrate to form a patterned photoresist layer on the substrate.	12-01-2011
20110300483	Self-Segregating Multilayer Imaging Stack With Built-In Antireflective Properties - A coating process comprises forming a patterned material layer on a substrate using a self-segregating polymeric composition comprising a polymeric photoresistive material and an antireflective coating material contained in a single solution. When depositing this solution on a substrate and removing the solvent, the two materials self-segregate into two layers. This produces a coated substrate having a uniaxial bilayer coating oriented in a direction orthogonal to the substrate with a top photoresistive coating layer and a bottom antireflective coating layer. Pattern-wise exposing the coated substrate to imaging radiation and contacting the coated substrate with a developer, produces the patterned material layer. Any optional top coat material and a portion of the photoresist layer can be simultaneously removed from the coated substrate to form a patterned photoresist layer on the substrate.	12-08-2011

Kanggou Cheng, Albany, NY US

Patent application number	Description	Published
20120193710	DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE - A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.	08-02-2012

Kangguo Cheng, Schenectay, NY US

Patent application number	Description	Published
20130099318	THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.	04-25-2013
20130099319	THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.	04-25-2013

Kangguo Cheng, Guiderland, NY US

Patent application number	Description	Published
20090230471	TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS - A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.	09-17-2009
20100102373	TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS - A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.	04-29-2010
20120241902	SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.	09-27-2012
20120319232	Self-Aligned Dual Depth Isolation and Method of Fabrication - FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.	12-20-2012

Patent applications by Kangguo Cheng, Guiderland, NY US

Kangguo Cheng, Hopewell Junction, NY US

Patent application number	Description	Published
20110169065	METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES - A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.	07-14-2011
20110254098	INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS - A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.	10-20-2011
20120190203	METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.	07-26-2012

Kangguo Cheng, Schenectady, NY US

Patent application number	Description	Published
20120064694	FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL - A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.	03-15-2012
20120146112	FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.	06-14-2012
20120205732	INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT - An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.	08-16-2012
20120235236	STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS - A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.	09-20-2012
20120235238	FULLY-DEPLETED SON - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.	09-20-2012
20120235239	HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.	09-20-2012
20120261754	MOSFET with Recessed channel FILM and Abrupt Junctions - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.	10-18-2012
20120261757	STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.	10-18-2012
20120261792	SOI DEVICE WITH DTI AND STI - An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer.	10-18-2012
20120280250	SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS - A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.	11-08-2012
20120286364	Integrated Circuit Diode - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.	11-15-2012
20120292700	Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same - An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.	11-22-2012
20120292705	SEMICONDUCTOR STRUCTURE HAVING UNDERLAPPED DEVICES - A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.	11-22-2012
20120299103	RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.	11-29-2012
20120302019	NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.	11-29-2012
20120306049	METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE - A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.	12-06-2012
20120313143	HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT - A floating body memory cell, memory circuit, and method for fabricating floating body memory cells. The floating body memory cell includes a bi-layer heterojunction having a first semiconductor coupled to a second semiconductor. The first semiconductor and the second semiconductor have different energy band gaps. The floating body memory cell includes a buried insulator layer. The floating body memory cell includes a back transistor gate separated from the second semiconductor of the bi-layer heterojunction by at least the buried insulated layer. The floating body memory cell also includes a front transistor gate coupled to the first semiconductor of the bi-layer heterojunction.	12-13-2012
20120326230	SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE - A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.	12-27-2012
20120326232	MOSFET WITH RECESSED CHANNEL FILM AND ABRUPT JUNCTIONS - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.	12-27-2012
20130011975	RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER - A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.	01-10-2013
20130015534	THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHSAANM Cheng; KangguoAACI SchenectadyAAST NYAACO USAAGP Cheng; Kangguo Schenectady NY USAANM Doris; Bruce B.AACI BrewsterAAST NYAACO USAAGP Doris; Bruce B. Brewster NY USAANM Khakifirooz; AliAACI Mountain ViewAAST CAAACO USAAGP Khakifirooz; Ali Mountain View CA USAANM Kulkarni; PranitaAACI SlingerlandsAAST NYAACO USAAGP Kulkarni; Pranita Slingerlands NY US - A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.	01-17-2013
20130032876	Replacement Gate ETSOI with Sharp Junction - A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.	02-07-2013
20130034938	REPLACEMENT GATE ETSOI WITH SHARP JUNCTION - A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.	02-07-2013
20130062702	CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.	03-14-2013
20130062704	CMOS STRUCTURE HAVING MULTIPLE THRESHOLD VOLTAGE DEVICES - A complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes a first transistor device and a second transistor device formed on a semiconductor substrate. A set of vertical oxide spacers selectively formed for the first transistor device are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.	03-14-2013
20130069159	Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.	03-21-2013
20130071979	Field Effect Transistor Device with Raised Active Regions - A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.	03-21-2013
20130075817	JUNCTIONLESS TRANSISTOR - A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.	03-28-2013
20130078777	METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR - A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.	03-28-2013
20130082306	ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.	04-04-2013
20130082308	SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.	04-04-2013
20130082311	SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS - Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.	04-04-2013
20130082328	ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS - Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.	04-04-2013
20130102119	BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.	04-25-2013
20130102130	BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.	04-25-2013

Kangguo Cheng, Yorktown Heights, NY US

Patent application number	Description	Published
20120256261	SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.	10-11-2012
20130012009	METHOD FOR SELF ALIGNED METAL GATE CMOS - A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.	01-10-2013
20130012010	SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.	01-10-2013
20130017667	SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME - A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.	01-17-2013

Keh-Shin F. Cheng, Mahopac, NY US

Patent application number	Description	Published
20090276378	System and Method for Identifying Document Structure and Associated Metainformation and Facilitating Appropriate Processing - A system and method for processing documents by utilizing the textual content and layout of the documents, including visual indicators, to more efficiently and reliably process the documents across various document types. The system and method identifies visually distinguishable elements within the document, such as section and sub-section boundary indicators, to mark, divide and label the boundaries and content type such that the sections are more clearly identifiable and easily processed. The system and method uses known elements, including section heading types, keywords, section type classifiers, sub-section heading constructs, stop words, and the like to adaptively identify and process a broad range of document types. The system and method continually refines and updates these known elements and allows users to discover and define new elements for further refinement and updating.	11-05-2009
20100274618	System and Method for Real Time Support for Agents in Contact Center Environments - A real-time method and system are described for automatically extracting text from the customer-agent interaction at a contact center, analyzing the extracted text to automatically identify one or more customer issues, and performing processing by contact-center agent buddies (CABs) to generate at least one response to the customer issues.	10-28-2010

Patent applications by Keh-Shin F. Cheng, Mahopac, NY US

Ken-Shin Cheng, Mahopac, NY US

Patent application number	Description	Published
20080215764	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-04-2008
20080216004	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-04-2008
20080222422	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-11-2008

Kuo-Chi Cheng, Armonk, NY US

Patent application number	Description	Published
20100286372	Pregnane X Receptor Compositions, Crystals and Uses Thereof - The present invention relates, inter alia, to PXR polypeptides and crystals that are useful, for example, for crystallization and in assays for identification of modulators of PXR.	11-11-2010

Lili Cheng, Rexford, NY US

Patent application number	Description	Published
20120027247	PINNED-CONTACT, OSCILLATING LIQUID-LIQUID LENS AND IMAGING SYSTEMS - An oscillating liquid lens and imaging system and method employing the lens are provided. The liquid lens includes a substrate with a channel opening extending through the substrate. A liquid drop is disposed within the channel and is sized with a first droplet portion, including a first capillary surface, protruding away from a first substrate surface, and a second droplet portion, including a second capillary surface, protruding away from a second substrate surface. The liquid lens further includes an enclosure at least partially surrounding the substrate, and including a chamber. The liquid drop resides within the chamber, and the liquid lens includes a second liquid disposed within the chamber in direct or indirect contact with the liquid drop, and the liquid lens further includes a driver for oscillating the liquid drop within the channel.	02-02-2012

Monsong Cheng, Katonah, NY US

Patent application number	Description	Published
20110274413	Multimedia control center - A video library is formed within a personal video depot (PVD). The PVD has capability to accept purchased video's and DVD's as well as personal video's captured on camcorders. The purchased video's and DVD's are rights verified and assigned to a user having an authenticated ID. The PVD has capability to play a selected video on a TV as well as acquire additional video titles from the server connected to the depot through a network. A menu is displayed on a TV from which a remote control is used to make selections that affect the purchase of video titles and operation of the PVD.	11-10-2011

Pau-Chen Cheng, Yorktown Heights, NY US

Patent application number	Description	Published
20080263662	SYSTEM AND METHOD FOR FUZZY MULTI-LEVEL SECURITY - An access control system and method includes a risk index module which computes a risk index for a dimension contributing to risk. A boundary range defined for a parameter representing each risk index such that the parameter above the range is unacceptable, below the range is acceptable and in the range is acceptable with mitigation measures. A mitigation module determines the mitigation measures which reduce the parameter within the range.	10-23-2008
20090055890	SYSTEM AND METHOD FOR SECURITY PLANNING WITH HARD SECURITY CONSTRAINTS - A method for security planning with hard security constraints includes: receiving security-related requirements of a network to be developed using system inputs and processing components; and generating the network according to the security-related requirements, wherein the network satisfies hard security constraints.	02-26-2009
20090282487	Method of Managing and Mitigating Security Risks Through Planning - An exemplary method is provided for managing and mitigating security risks through planning. A first security-related information of a requested product is received. A second security-related information of resources that are available for producing the requested product is received. A multi-stage process with security risks managed by the first security-related information and the second security-related information is performed to produce the requested product.	11-12-2009
20100332422	Policy Evolution With Machine Learning - A method for constructing a classifier which maps an input vector to one of a plurality of pre-defined classes, the method steps includes receiving a set of training examples as input, wherein each training example is an exemplary input vector belonging to one of the pre-defined classes, learning a plurality of functions, wherein each function maps the exemplary input vectors to a numerical value, and determining a class for the input vector by combining numerical outputs of the functions determined for the input vector.	12-30-2010
20110173084	Risk Adaptive Information Flow Based Access Control - Systems and methods are provided to manage risk associated with access to information within a given organization. The overall risk tolerance for the organization is determined and allocated among a plurality of subjects within the organization. Allocation is accomplished using either a centralized, request/response or free market mechanism. As requested from subjects within the organization for access to objects, i.e. information and data, are received, the amount of risk or risk level associated with each requested is quantified. Risk quantification can be accomplished using, for example, fuzzy multi-level security. The quantified risk associated with the access request in combination with the identity of the object and the identity of the subject are used to determine whether or not the request should be granted, denied or granted with appropriated mitigation measures.	07-14-2011

Patent applications by Pau-Chen Cheng, Yorktown Heights, NY US

Perry Cheng, Yorktown Heights, NY US

Patent application number	Description	Published
20090300086	SCHEDULING AND PERFORMING GARBAGE COLLECTION IN A REAL-TIME SYSTEM WITH GUARANTEED SPACE BOUNDS - A method for performing garbage collection for a real-time application uses a memory for determining an amount of memory required to run the garbage collection process and waits until the determined amount of memory is available, then allocates memory space for the application by segmenting the memory space into a number of pages of a predetermined size. A mutator is used for assuring that only non-null, unmarked objects are placed into a write buffer. A hybrid collector is used for removing the dead objects and defragmenting the memory space.	12-03-2009

Perry Cheng, New York, NY US

Patent application number	Description	Published
20100100575	Lock Deferral for Real-Time Garbage Collection - Techniques are disclosed for schedule management. By way of example, a method for managing performance of tasks of a thread associated with a processor comprises the following steps. A request to execute a task of a first task type within the thread is received. A determination is made whether the processor is currently executing a critical section of a task of a second task type within the thread. When it is determined that the processor is not executing a critical section of the second task type within the thread, the task of the first task type is executed within the thread. When it is determined that the processor is executing a critical section of the first task type within the thread, a determination is made whether the request for execution of the task of the first task type within the thread is deferrable based on a prior execution of one or more units of the first task type. The first task type may be an overhead task type such as a garbage collection task type, and the second task type may be an application task type.	04-22-2010
20100107168	Scheduling for Real-Time Garbage Collection - Techniques are disclosed for schedule management. By way of example, a method for managing performance of tasks in threads associated with at least one processor comprises the following steps. One or more units of a first task type are executed. A count of the one or more units of the first task type executed is maintained. The count represents one or more credits accumulated by the processor for executing the one or more units of a first task type. One or more units of a second task type are executed. During execution of the one or more units of a second task type, a request to execute at least one further unit of the first task type is received. The amount of credits in the count is checked. When it is determined that there is sufficient credit in the count, the request to execute the at least one further unit of the first task type is forgone, and execution of the one or more units of the second task type continues. When it is determined that there is insufficient credit in the count, the at least one further unit of the first task type is executed. The first task type may be an overhead task type such as a garbage collection task type, and the second task type may be an application task type.	04-29-2010

Perry Cheng, New City, NY US

Patent application number	Description	Published
20090049282	SYSTEM AND METHOD FOR MANAGING DATA - A method of performing data and pointer compression includes, in a buffer which is formed between a processor and a level one cache and stores plural tags and full-word values associated with the tags, when the buffer is presented with an address, breaking the address into a line number which indexes a set of the full-word values, and a tag which is used as a key to determine whether a value in the set of full-word values includes a value associated with the presented address, if a tag in the presented address matches a tag in the buffer, returning a full-word value in the buffer which is associated with the tag, and storing the returned full-word value in a destination register of an instruction which originated the presented address, and if a tag in the presented address does not match a tag in the buffer, generating a fault and branching control to a pre-defined handler.	02-19-2009

Patent applications by Perry Cheng, New City, NY US

Perry Cheng, New York City, NY US

Patent application number	Description	Published
20100262636	GARBAGE COLLECTOR WITH EAGER READ BARRIER - A garbage collection system that needs to meet real-time requirements uses an eager read barrier that performs a forwarding operation as soon as a quantity is loaded. The barrier maintains a to-space invariant by including a forwarding pointer in the header of objects to be moved or accessed that normally points to the object itself. However, if the object has been moved, the forwarding pointer points to the new object location. The eager read barrier maintains the registers and stack cells such that the registers and stack cells always point into to-space. Barrier-sinking and common sub-expression elimination are used to minimize the overhead associated with the read barrier.	10-14-2010

Perry Sze-Din Cheng, New York City, NY US

Patent application number	Description	Published
20100198885	METHOD AND SYSTEM FOR EXECUTING A TASK AND MEDIUM STORING A PROGRAM THEREFOR - A method of executing a task includes executing, by using a processor, a first task including a low-frequency task in which garbage is collected using a garbage collector, initializing a second task including a high-frequency task by constructing an instance of a class that implements a standard runnable thread interface, and creating a data structure for supporting communication between the second task and lower priority threads, the data structure being accessible by a thread running in a garbage-collected heap in the first task to communicate data between the high-frequency task and the low-frequency task, validating the second task to ensure that the second task is executable without synchronizing with the first task, instantiating the second task to create a class for executing the second task; and after the instantiating the second task, executing the second task, the garbage collector being preemptable by the second task.	08-05-2010

Shuhua Cheng, New York, NY US

Patent application number	Description	Published
20100055116	Methods and Compositions for Targeting c-Rel - The present invention relates to compositions and methods for targeting c-Rel. In particular, the present invention provides compositions and methods for treating cancers, inflammatory diseases, autoimmune diseases, and transplant rejection by inhibiting c-Rel activity and for regulating c-Rel for research and drug screening applications.	03-04-2010

Tammy Cheng, Flushing, NY US

Patent application number	Description	Published
20100276721	Light Emitting Device Encapsulated with Silicones and Curable Silicone Compositions for Preparing the Silicones - A composition includes: (I) an alkenyl functional, phenyl-containing polyorganosiloxane, an Si—H functional phenyl-containing polyorganosiloxane, or a combination thereof; (II) a hydrogendiorganosiloxy terminated oligodiphenylsiloxane having specific molecular weight, an alkenyl-functional, diorganosiloxy-terminated oligodiphenylsiloxane having specific molecular weight, or a combination thereof; and (III) a hydrosilylation catalyst. A light emitting device is made by applying the composition onto a light source followed by curing. The composition provides a cured material with mechanical properties suited for use as an encapsulant for a light emitting device.	11-04-2010
20110221060	Process for Fabricating Electronic Components Using Liquid Injection Molding - A process for fabricating an electronic component includes a liquid injection molding method for overmolding a semiconductor device. The liquid injection molding method includes: i) placing the semiconductor device in an open mold, ii) closing the mold to form a mold cavity, iii) heating the mold cavity, iv) injection molding a curable liquid into the mold cavity to overmold the semiconductor device, v) opening the mold and removing the product of step iv), and optionally vi) post-curing the product of step v). The semiconductor device may have an integrated circuit attached to a substrate through a die attach adhesive.	09-15-2011

Tien Cheng, Bedford, NY US

Patent application number	Description	Published
20100038793	INTERCONNECT STRUCTURES COMPRISING CAPPING LAYERS WITH LOW DIELECTRIC CONSTANTS AND METHODS OF MAKING THE SAME - Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising Si	02-18-2010

Tien-Jen Cheng, Bedford, NY US

Patent application number	Description	Published
20090163019	FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING - A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.	06-25-2009
20100038789	CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS - A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.	02-18-2010
20120061234	Deposition Chamber Cleaning Method Including Stressed Cleaning Layer - A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.	03-15-2012
20120267785	METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY - Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.	10-25-2012
20130095649	Chemical Bath Replenishment - Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath.	04-18-2013

Patent applications by Tien-Jen Cheng, Bedford, NY US

Tien-Jen Cheng, Hopewell Junction, NY US

Patent application number	Description	Published
20110162875	SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION - A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.	07-07-2011
20110183520	Method for Removing Copper Oxide Layer - The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.	07-28-2011

Tien-Jen J. Cheng, Bedford, NY US

Patent application number	Description	Published
20120068315	METHOD OF IMPROVING MECHANICAL PROPERTIES OF SEMICONDUCTOR INTERCONNECTS WITH NANOPARTICLES - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.	03-22-2012
20120146224	Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.	06-14-2012

Ting Cheng, Mahopac, NY US

Patent application number	Description	Published
20080215764	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-04-2008
20080216004	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-04-2008
20080222422	MANAGING ELECTRONIC DOCUMENTS UTILIZING A DIGITAL SEAL - A method for storing electronic documents can include associating a digital seal with at least one electronic document. An image within a user interface can be displayed, wherein the image is a user selectable representation for the digital seal. At least one metadata attribute can be stored as a characteristic related to the digital seal. A storage characteristic of at least one electronic document can be modified based on one or more of the metadata attributes.	09-11-2008

Tong Cheng, Webster, NY US

Patent application number	Description	Published
20080305100	Activated Protein C Inhibits Undesirable Effects of Plasminogen Activator in the Brain - Activated protein C (APC), a prodrug, and/or a variant of APC may be used to inhibit undesirable effects of plasminogen activator: e.g., apoptosis or cell death of neurons and endothelial cells, brain hemorrhage or intracerebral bleeding, and/or tissue damage in a subject's brain. Inhibition appears to act through the extrinsic pathway of death receptor signal transduction. This represents an improvement in treatment using plasminogen activator (e.g., fibrinolysis). By reducing undesirable effects, the window for fibrinolytic therapy by plasminogen activator may be widened.	12-11-2008

Winnie Wing-Yee Cheng, Tarrytown, NY US

Patent application number	Description	Published
20120259962	REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS - Aspects of the present invention dynamically reduce a frequency at which IT infrastructure automatically generates alerts. Historical data across a plurality of data sources in the IT infrastructure is analyzed. An opportunity to reduce the frequency at which the IT infrastructure automatically generates the alerts is identified. A new alert policy addressing the opportunity to reduce alert frequency is generated. An impact of the new alert policy on a set of predefined service level objectives (SLOs) and service level agreements (SLAs) is evaluated. The new alert policy is deployed in the IT infrastructure.	10-11-2012

Yuan Fang Cheng, Forrest Hills, NY US

Patent application number	Description	Published
20090004955	SANDING APPARATUS WITH MOLDED ELASTOMERIC PAD - A sander comprises a body member molded of polypropylene to which a soft pad member is integrally molded or directly bonded thereto. Preferably, the material comprising the pad member is of a thermoplastic elastomer material, such as Santoprene®. Significantly, when the pad member is molded directly to the body member, the pad has internal dimensions only slightly larger than the external dimensions of the body member so that, when the body member is located within the confines of the pad member, a secure fit is formed between these two members, without any space between them. Further, the respective dimensions of the body member and pad member give the sander a thick, one-piece appearance in side and end views. The pad member may also include a plurality of openings which help provide a “spongy” effect to the user, smoothing the peaks and reaching the valleys of an uneven surface upon which the sander is utilized.	01-01-2009
20100048111	SANDING APPARATUS WITH MOLDED ELASTOMERIC PAD - A sander comprises a body member molded of polypropylene to which a soft pad member is integrally molded or directly bonded thereto. Preferably, the material comprising the pad member is of a thermoplastic elastomer material, such as Santoprene®. Significantly, when the pad member is molded directly to the body member, the pad has internal dimensions only slightly larger than the external dimensions of the body member so that, when the body member is located within the confines of the pad member, a secure fit is formed between these two members, without any space between them. Further, the respective dimensions of the body member and pad member give the sander a thick, one-piece appearance in side and end views. The pad member may also include a plurality of openings which help provide a “spongy” effect to the user, smoothing the peaks and reaching the valleys of an uneven surface upon which the sander is utilized.	02-25-2010

Patent applications by Yuan Fang Cheng, Forrest Hills, NY US

Yuan Fang Cheng, Forest Hills, NY US

Patent application number	Description	Published
20080272269	HOOK FOR PAINT CAN AND PAINT BRUSH - An inventive elongated, generally horizontally oriented hook that is used to simultaneously carry a paint can and a paint brush at the waist of a user in order to liberate one or more of the hands, to alleviate fatigue and/or to prevent accidents. In a preferred embodiment, the hook has a clip portion which allows the hook to be removably attached to the belt or directly to the pants of a user. The hook further comprises a proximal bend and a distal bend, the former of which can be removably engaged to the bail of a paint can, while the latter can removably engage a paint brush. In one preferred embodiment, the elongated hook is made with a single piece of cylindrical wire.	11-06-2008
20090255129	MULTIFUNCTION CARTON TRAY CUTTER - A guided utility knife that alternates between a carton tray cutter and a conventional utility knife is provided herewith. The knife comprises two rotatable guide portions that are hingedly attached to the housing. Each guide portion flips laterally, away from the cutting blade from its unfolded position to its folded position. Each guide portion further occupies a channel on the exterior surface of the housing. Magnets are provided in the housing to secure the guide portions in both the folded and unfolded positions.	10-15-2009
20110167647	CUTTING IMPLEMENTS - A folding knife for applying a cutting action is provided that includes a blade assembly having a guard configured to cover the cutting edge of the blade when the knife is not in use. The guard is maintained in a normally blade covered position by a resilient member. The blade guard has a guard actuator for providing at least one motion for a user to move the blade guard from the normally blade covered position to an un-guarded or cutting position. The folding knife comprises a housing having the blade assembly locked in a closed position and is pivotably associated with the housing. The knife further comprises an actuator for unlocking the blade assembly from the closed position to a locked open position. The actuator further comprises a locking tab and the blade assembly further comprises a locking slot. The locking tab is configured to lock the blade guard in the un-guarded or cutting position. The housing further comprises a resilient member urging the blade assembly in the open position. Upon depression of the actuator, the blade assembly will automatically open to the locked open position from the locked closed position. Other embodiments are also described.	07-14-2011
20110203064	Multifunction Caulk Tool - A preferred embodiment of a caulk tool comprises a body member having a raised handle and two working heads. The first working head is adapted for the application of caulk and is connected to the first descending end of the raised handle. The first working head preferably comprises a triangular member formed of soft plastic material. The triangular member is rotatable, having three tips of varying size. The second working head is adapted for the removal of old caulk and is connected to the second descending end of the raised handle axially opposed to the first working head. The second working head preferably comprises a metallic head having two tips suited to remove old caulk. In a preferred embodiment, a third working head in the form of a flat scraper is positioned adjacent to said second working head.	08-25-2011
20130008036	RAZOR BLADE ASSEMBLY - There is provided in a preferred embodiment of the present invention a razor blade assembly having two plastic blades affixed to a central metal core. Each blade includes a blade edge and a connector for connecting to a connection slot in the metal core.	01-10-2013

Patent applications by Yuan Fang Cheng, Forest Hills, NY US

Yu- Ting Cheng, Elmsford, NY US

Patent application number	Description	Published
20090302454	Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer - The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.	12-10-2009

Yu-Wei Cheng, Forest Hills, NY US

Patent application number	Description	Published
20100144867	USE OF LECITHIN:RETINOL ACYL TRANSFERASE GENE PROMOTER METHYLATION IN EVALUATING THE CANCER STATE OF SUBJECT - The present invention relates to a method of evaluating the cancer state of a subject using lecithin:retinol acyl transferase (LRAT) gene promoter methylation status. Methods of analyzing and quantifying LRAT gene promoter methylation level are also disclosed. The present invention also relates to methods of determining the prognosis for s subject having cancer by assessing LRAT mRNA expression and LRAT protein expression. Methods of cancer detection, diagnosis, prognosis, and treatment are also disclosed.	06-10-2010

Zhen Z. Cheng, Elmhurst, NY US

Patent application number	Description	Published
20090292119	METHODS FOR SYNTHESIZING BENZOTHIAZEPINE COMPOUNDS - The present invention provides improved methods for synthesizing novel benzothiazepine compounds. In particular, the invention relates to a new method that generally is used to make the substituted 2,3,4,5-tetrahydro-1,4-benzothiazepine compounds of a general formula	11-26-2009

Patent applications by Zhen Z. Cheng, Elmhurst, NY US

Zhen Zhuang Cheng, Elmhurst, NY US

Patent application number	Description	Published
20100152440	NOVEL ANTI-ARRHYTHMIC AND HEART FAILURE DRUGS THAT TARGET THE LEAK IN THE RYANODINE RECEPTOR (RyR2) - The present invention provides novel 1,4-benzothiazepine intermediates and derivatives, methods for synthesizing same, and methods for assaying same. The present invention also provides methods for using these novel compounds to limit or prevent a decrease in the level of RyR2-bound FKBP12.6 in a subject; to prevent exercise-induced sudden cardiac death in a subject; and to treat or prevent heart failure, atrial fibrillation, or exercise-induced cardiac arrhythmia in a subject. The present invention further provides methods for identifying an agent that enhances binding of RyR2 and FKBP12.6, and agents identified by these methods. Additionally, the present invention provides methods for identifying agents for use in treating or preventing heart failure, atrial fibrillation, or exercise-induced cardiac arrhythmia, and in preventing exercise-induced sudden cardiac death. Also provided are agents identified by such methods.	06-17-2010

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