Patent application number | Description | Published |
20080299740 | METHOD FOR FORMING STI STRUCTURE - A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned mask layer as a mask to form a trench in the substrate, and then the trench is filled with an insulating material. | 12-04-2008 |
20080308857 | Systems and Methods for Self Convergence During Erase of a Non-Volatile Memory Device - A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle. | 12-18-2008 |
20080315287 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness. | 12-25-2008 |
20090046516 | DATA WRITING METHOD FOR FLASH MEMORIES - A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage. | 02-19-2009 |
20100025750 | MEMORY AND METHOD OF FABRICATING THE SAME - A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å. | 02-04-2010 |
20100202179 | MEMORY DEVICE - A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line. | 08-12-2010 |
20100323483 | METHOD OF FABRICATING MEMORY - A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure. | 12-23-2010 |
20110062507 | SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates. | 03-17-2011 |
20110156102 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line. | 06-30-2011 |
20120273842 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line. | 11-01-2012 |