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| 20110156267 | Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element - The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking. | 06-30-2011 |
| 20110156268 | Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element - The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor process includes the following steps: (a) providing a semiconductor element including a silicon base material and at least one conductive via structure disposed in the silicon base material; (b) removing part of the silicon base material to form a first surface, wherein the conductive via structure protrudes from the first surface of the silicon base material so as to form a through via structure; (c) forming a protective layer on the first surface of the silicon base material to cover the through via structure, wherein the protective layer is made of photo-sensitive material; (d) removing part of the protective layer to form a first surface, so as to expose the through via structure on the first surface of the protective layer. Whereby, the protective layer disposed on the through via structure is totally removed, so that the yield rate of electrically connecting the through via structure and external elements is ensured. | 06-30-2011 |
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| 20090041997 | PU COMPOSITE AND METHOD OF FABRICATING THE SAME - A PU composite and a method of fabricating the same are provided. The fabrication method includes: (a) providing a release paper; (b) coating a fabric layer on the release paper, the fabric layer containing a PU resin, an abrasion resistant, and a colorant; (c) drying the fabric layer; (d) coating a first laminated layer on the fabric layer; (e) drying the first laminated layer; (f) laminating a wet PU foam layer on the first laminated layer; (g) releasing the release paper to form a semi-product; (h) providing a plastic layer, which is of a thermoplastic; (i) coating a second laminated layer on the plastic layer; (j) drying the second laminated layer; and (k) laminating the semi-product of Step (g) on the second laminated layer, so as to form a PU composite. Compared with conventional PU composites, the PU composite of the present invention has better UV resistance, solvent resistance, and abrasion resistance. | 02-12-2009 |
| 20110168323 | PU COMPOSITE AND METHOD OF FABRICATING THE SAME - A PU composite and a method of fabricating the same are provided. The fabrication method includes: (a) providing a release paper; (b) coating a fabric layer on the release paper, the fabric layer containing a PU resin, an abrasion resistant, and a colorant; (c) drying the fabric layer; (d) coating a first laminated layer on the fabric layer; (e) drying the first laminated layer; (f) laminating a wet PU foam layer on the first laminated layer; (g) releasing the release paper to form a semi-product; (h) providing a plastic layer, which is of a thermoplastic; (i) coating a second laminated layer on the plastic layer; (j) drying the second laminated layer; and (k) laminating the semi-product of Step (g) on the second laminated layer, so as to form a PU composite. Compared with conventional PU composites, the PU composite of the present invention has better UV resistance, solvent resistance, and abrasion resistance. | 07-14-2011 |
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| 20100244758 | FAN DEVICE WITH IMPROVED SPEED CONTROL MODULE AND PLURAL FAN SYSTEM CONSTRUCTED THEREBY - A fan device with improved speed control module includes a stator, a rotor, and a speed control module. The stator has a driving unit outputting currents for the stator to generate alternative magnetic fields and thus turn the rotor. The speed control module includes a control unit and a speed adjusting circuit, with the control unit generating a control command for the driving unit and further outputting a state signal for the speed adjusting circuit to control whether a PWM signal enters the control circuit or not. | 09-30-2010 |
| 20110070098 | FAN CONTROL SYSTEM - The present invention relates to a fan control system. The fan control system includes a first micro controller, a second micro controller and a first logic circuit. The first micro controller provides at least one first control signal. The second micro controller is connected to the first micro controller. The second micro controller detects operational status of the first micro controller, and provides at least one second control signal. The first logic circuit receives the first control signal and the second control signal to process logic operation and to generate at least one driving signal to fan. The fan control system of the invention utilizes two micro controllers, when one of the two micro controllers malfunctions, the first logic circuit allows the other micro controller to continue proper operation of the fan, thereby preventing the problem of insufficient heat dissipation that results from malfunction of the single micro controller of a conventional fan control system. | 03-24-2011 |
| 20110101776 | LAMP CIRCUIT - A lamp circuit is disclosed, comprising a direct current (DC) power supplier adapted to provide a supply voltage, a driving unit coupled to the DC power supplier so as to receive the supply voltage, and a light-radiating module coupled to the driving unit and having a DC output side. The driving unit generates a constant DC current that passes through the light-radiating module such that a DC voltage to be supplied to a DC load is built at the DC output side. | 05-05-2011 |
| 20110175537 | AC LED LAMP - An alternating current (AC) light-emitting diode (LED) lamp includes a first AC power end, a second AC power end, a lighting module and a direct current (DC) power output circuit. The lighting module has a first end, a second end and at least one LED unit, wherein the first end is electrically coupled to the first AC power end. The at least one LED unit has one or more LEDs connected in series. The DC power output circuit has a first end and a second end, wherein the second end of the DC power output circuit is electrically coupled to the second AC power end, while the first end of the DC power output circuit is electrically coupled to the second end of the lighting module. The DC power output circuit has a DC output side. | 07-21-2011 |
| 20110187299 | FAN SYSTEM AND BRAKING CIRCUIT THEREOF - A fan system comprising a motor, a motor driving circuit and a control unit is disclosed. The motor driving circuit is coupled to the motor. The control unit is coupled to the motor driving circuit, generates a forward rotation command for controlling the motor to rotate in a predetermined direction when the control unit receives electrical power, and generates a backward rotation command for controlling the motor to rotate in a direction opposite to the predetermined direction when the control unit fails to receive the electrical power. | 08-04-2011 |
| 20110221364 | ROTATION CONTROL CIRCUIT OF FAN - A rotation control circuit comprises a motor-driving unit and a rotation-switching unit. The motor-driving unit is coupled to a motor of a fan. The rotation-switching unit is coupled to the motor-driving unit and has at least a charging-discharging circuit for generating a rotation control command, the rotation control command controls the motor to rotate in a forward direction for a time period when the motor starts to operate, and controls the motor to rotate in a backward direction opposite to the forward direction. | 09-15-2011 |
| 20110254490 | MOTOR-DRIVING APPARATUS - A motor-driving apparatus, comprising a main driving unit having a plurality of main current-driving ends coupled to a stator coil of a motor, a detection control unit coupled to the main driving unit, and an auxiliary driving unit coupled to the detection control unit and having a plurality of auxiliary current-driving ends. Wherein, the number of the main current-driving ends is the same as that of the auxiliary current-driving ends, and each of the main current-driving ends is connected to a respective one of the auxiliary current-driving ends in parallel. | 10-20-2011 |
| 20110266989 | MOTOR SYSTEM - A motor system comprises a motor and a driving module. The motor has a plurality coil units not electrically connected to each other. The driving module has a control unit, a driving unit and a circuit board. The control unit is coupled to the driving unit. The driving unit has a plurality of driving circuits. The number of the driving circuits is the same as the number of the coil units. Each of the driving circuits is coupled to a respective one of the coil units so as to form a plurality of independent coil loops. The control unit and the driving unit are mounted on the circuit board. | 11-03-2011 |
| 20110292614 | Cooling Module Assembly Method - A cooling module assembly method comprises forming at least one through-hole on a circuit board; coupling the circuit board to a heat dissipating unit so that a face of the circuit board is coupled to a coupling face of the heat dissipating unit; filling the at least one through-hole with metal solders; fixing at least one heat-generating element to another face of the circuit board, wherein the at least one heat-generating element aligns with and covers the at least one through-hole; and soldering the at least one heat-generating element and the heat dissipating unit together by melting the metal solders in the at least one through-hole. | 12-01-2011 |
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| 20090152721 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 06-18-2009 |
| 20100051341 | Circuit substrate having power/ground plane with grid holes - The present invention relates to a circuit substrate having a first conductive layer. The first conductive layer includes at least one power/ground plane. The power/ground plane includes at least one plane edge and plurality of grid lines. Each grid line has a width. The grid lines intersect each other to define a plurality of first grid holes, wherein the distance between the first grid hole that is closest to the plane edge and the plane edge is 1.5 times the width. Thus, the influence on the resistance of power signal and ground signal caused by the first grid holes is reduced, power integrity is improved, and heat generation is reduced. | 03-04-2010 |
| 20100065312 | Substrate for window ball grid array package - The present invention relates to a substrate for a window ball grid array package. The substrate has at least one window, a plurality of fingers and at least one power/ground section (or power/ground ring). The window penetrates the substrate. The fingers are disposed at the periphery of the window. The power/ground section (or power/ground ring) is disposed between the fingers and the window. The power/ground section (or power/ground ring) is connected to a power/ground voltage so that the power/ground section (or power/ground ring) can improve the smoothness of the current and power integrity, and reduce the heat generation. | 03-18-2010 |
| 20100071939 | Substrate of window ball grid array package - The present invention relates to a substrate of a window ball grid array package. The substrate includes at least one window, a first conductive layer, a second conductive layer, a dielectric layer, a plurality of first vias and a plurality of second vias. The window penetrates the substrate. The first conductive layer has a plurality of fingers and at least one first power/ground plane, and the fingers are disposed at the periphery of the window. The second conductive layer has at least one second power/ground plane. The dielectric layer is disposed between the first conductive layer and the second conductive layer. The first vias electrically connect the first power/ground plane to the second power/ground plane. The second vias are disposed between the fingers and the window, and electrically connect some of the fingers to the second power/ground plane. Thus, the substrate can control the characteristic impedance and increase the signal integrity. | 03-25-2010 |
| 20100102447 | Substrate of window ball grid array package and method for making the same - The present invention relates to a substrate of a window ball grid array package and a method for making the same. The substrate includes a core layer, a first conductive layer, a second conductive layer, at least one window and at least one via. The window includes a first through hole and a third conductive layer. The first through hole penetrates the substrate and has a first sidewall. The third conductive layer is disposed on the first sidewall and connects the first conductive layer and the second conductive layer. The via includes a second through hole and a fourth conductive layer. The second through hole penetrates the substrate and has a second sidewall. The fourth conductive layer is disposed on the second sidewall and connects the first conductive layer and the second conductive layer. As a result, the substrate has the effect of controlling the characteristic impedance and increasing the signal integrity. | 04-29-2010 |
| 20100283139 | Semiconductor Device Package Having Chip With Conductive Layer - The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. | 11-11-2010 |
| 20110237032 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 09-29-2011 |
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| 20080202705 | Cordless Blinds with Secondary Blind Adjustment Means - A cordless window covering system with a secondary mechanism to adjust the position of the window covering, to allow manual adjustment of the window covering when the bottom bar is out of reach by hand. In one embodiment, the secondary adjustment system includes a hooked hand tool that engages with a loop in the bottom bar. In another embodiment, the secondary adjustment system includes an exposed beaded corded coupled to the internal mechanisms of the system, so that pulling of beaded cord causes internal mechanisms to move and adjust the position of the window covering. | 08-28-2008 |
| 20080277075 | Window covering device - A window covering device without cord control comprising a top elongated member, a middle elongated member, a bottom elongated member, a window covering, a middle elongated member controller, a bottom elongated member controller, a window covering is connected between the middle elongated member and the bottom elongated member, the middle elongated member controller is mounted in the top elongated member, with a connection cord extending through the bottom elongated member, the window covering, the middle elongated member, and connected with the top elongated member. The window covering device can be opened from top or from bottom without cord control. | 11-13-2008 |
| 20080277076 | Window covering device - A window covering device has a top elongated member, a middle elongated member, and a bottom elongated member. A window covering is mounted between the middle elongated member and the bottom elongated member. A middle elongated member controller is mounted in the top elongated member, and is connected with the middle elongated member through the top elongated member by the connection cord. A bottom elongated member controller is mounted in the bottom elongated member, and is connected with the top elongated member through the bottom elongated member, the window covering and the middle elongated member by the connection cord. The middle elongated member controller has a cord seat with a spiral spring, the cord seat has connection cord, and connected with the middle elongated member through the top elongated member, in order to control the middle elongated member. | 11-13-2008 |
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| 20110278739 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased. | 11-17-2011 |
| 20110291690 | Apparatus and Method for Testing Non-Contact Pads of a Semiconductor Device to be Tested - The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening. Whereby, the non-contact pads of the semiconductor device to be tested face but not in physically contact with the testing pads of the active chip, so as to test the proximity communication between the non-contact pads of the semiconductor device and the testing pads of the active chip. | 12-01-2011 |
| 20110298139 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the strength of the first chip and the second chip is increased after being mounted to the substrate, so the yield of the semiconductor package is increased. | 12-08-2011 |
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| 20080303167 | DEVICE HAVING HIGH ASPECT-RATIO VIA STRUCTURE IN LOW-DIELECTRIC MATERIAL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar. | 12-11-2008 |
| 20090047782 | METHOD FOR MANUFACTURING A DEVICE HAVING A HIGH ASPECT RATIO VIA - Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched. | 02-19-2009 |
| 20100052136 | Three-Dimensional Package and Method of Making the Same - A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder. | 03-04-2010 |
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| 20080230887 | SEMICONDUCTOR PACKAGE AND THE METHOD OF MAKING THE SAME - The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased. | 09-25-2008 |
| 20090278253 | Semi-finished package and method for making a package - The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased. | 11-12-2009 |
