| Patent application number | Description | Published |
|---|
| 20080247249 | Circuit and method for a sense amplifier - A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided. | 10-09-2008 |
| 20090290446 | Memory Word-line Tracking Scheme - A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter. | 11-26-2009 |
| 20100103719 | Two-Stage 8T SRAM Cell Design - An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node. | 04-29-2010 |
| 20100238753 | INTEGRATED CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING LEAKAGE CURRENTS IN A RETENTION MODE - An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage. | 09-23-2010 |
| 20100259999 | KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter. | 10-14-2010 |
| 20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 01-27-2011 |
| 20110019460 | MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines. | 01-27-2011 |
| 20110063894 | SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line | 03-17-2011 |
| 20110090753 | POWER MANAGEMENT - An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power. | 04-21-2011 |
| 20110158007 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 06-30-2011 |
