Patent application number | Description | Published |
20080197438 | Sensor semiconductor device and manufacturing method thereof - This invention discloses a sensor semiconductor device and a manufacturing method thereof, including: providing a wafer having a plurality of sensor chips, forming a plurality of grooves between bond pads on active surfaces of the adjacent sensor chips; forming conductive traces in the grooves for electrically connecting the bond pads; mounting a transparent medium on the wafer for covering sensing areas of the sensor chips; thinning the sensor chips from the non-active surfaces down to the grooves, thereby exposing the conductive traces; cutting the wafer to separate the sensor chips; mounting the sensor chips on a substrate module having a plurality of substrates, electrically connecting the conductive traces to the substrates; providing an insulation material on the substrate module and between the sensor chips so as to encapsulate the sensor chips but expose the transparent medium; and cutting the substrate module to separate a plurality of resultant sensor semiconductor devices. | 08-21-2008 |
20080213942 | Method for fabricating semiconductor device and carrier applied therein - This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs. | 09-04-2008 |
20080224289 | Multi-chip stack structure and fabrication method thereof - A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented. | 09-18-2008 |
20080237767 | Sensor-type semiconductor device and manufacturing method thereof - A sensor-type semiconductor device and manufacturing method thereof are disclosed. The method includes providing a wafer comprising a plurality of sensor chips; forming concave grooves between the solder pads formed on the active surface of adjacent sensor chips; filling a filling material into the concave grooves and forming first conductive circuits electrically connecting the solder pads of adjacent sensor chips; mounting a light permeable body on the active surface of the wafer and thinning the non-active surface of the wafer to expose the filling material; mounting the wafer on a carrier board with second conductive circuits formed thereon corresponding in position to the filling material; forming first openings by cutting the light permeable body and the wafer to a position at which the second conductive circuits are located; forming metallic layers in the first openings by electroplating, the metallic layers electrically connecting the first and second conductive circuits of adjacent sensor chips; forming second openings by cutting the metallic layers to break the first conductive circuit connections and the second conductive circuit connections of adjacent sensor chips and meanwhile keep the first and second conductive circuits of each sensor chip still electrically connected through the metallic layers; filling a dielectric material into the second openings and removing the carrier board; and separating each of the sensor chips to form a plurality of sensor-type semiconductor devices. The invention overcomes the drawbacks of the prior art such as slanting notches formed on the non-active surface of the wafer, displacement of the notches due to the difficulty in precise alignment, as well as broken joints caused by concentrated stress generated in the slanting notches and exposed circuits. | 10-02-2008 |
20080246142 | Heat dissipation unit and a semiconductor package that has the heat dissipation unit - A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process. | 10-09-2008 |
20080251910 | Fabricating method of semiconductor package and heat-dissipating structure applicable thereto - A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure has a heat spreader having a size larger than that of the predetermined size of the semiconductor package, a covering layer formed on the, and a plurality of protrusions formed on edges of the covering layer that are free from being corresponding in position to the semiconductor chip, such that the protrusions can abut against a top surface of the mold cavity to prevent the heat spreader from being warped; and finally performing a singulation process according to the predetermined size and removing the encapsulant formed on the covering layer to form the desired semiconductor package. Also, this invention discloses a heat-dissipating structure applicable to the method described above. | 10-16-2008 |
20080251937 | Stackable semiconductor device and manufacturing method thereof - A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided. | 10-16-2008 |
20090014860 | Multi-chip stack structure and fabricating method thereof - A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products. | 01-15-2009 |
20090102063 | Semiconductor package and method for fabricating the same - This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost. | 04-23-2009 |
20090261476 | Semiconductor device and manufacturing method thereof - A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface. | 10-22-2009 |