Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Cheng, Hsinchu City
C. H. Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080217719 | Method For Reducing Crosstalk In Image Sensors Using Implant Technology - The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy. | 09-11-2008 |
Chang-Kai Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
Chao-Chen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080308829 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 12-18-2008 |
| 20100258834 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 10-14-2010 |
| 20110101400 | LIGHT EMITTING DIODES (LEDS) WITH IMPROVED LIGHT EXTRACTION BY ROUGHENING - Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device. | 05-05-2011 |
Chen-Chin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110118973 | IMAGE PROCESSING METHOD AND SYSTEM - An image processing method and a system are provided. The image processing method of moving camera comprises the following steps. An image of a road is captured by a first camera unit. A coordinate of the image of an object shown in the image of the road is captured when the image of the object shown in the image of the road is selected. At least an aiming angle of a second camera unit is adjusted according to the coordinate to make the field-of-view of the second camera unit aligned with the object. The image of the object is captured by the second camera unit. The image of the object is enlarged. | 05-19-2011 |
| 20110141279 | SURVEILLANCE CAMERA SYSTEM AND METHOD - A surveillance camera system including an optical imaging apparatus, a first reflective device and a second reflective device is provided. The optical imaging apparatus is capable of switching between a first magnification level and a second magnification level. The first reflection device is disposed at a position relative to the optical imaging apparatus for guiding a first field of view into the optical imaging apparatus, wherein the first reflective device has an opening region. The second reflective device is disposed within the opening region of the first reflection device for guiding a second field of view into the optical imaging apparatus. The second reflection device can have a relative motion relative to the first reflection device. | 06-16-2011 |
Cheng-Liang Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090159322 | THROUGH HOLE CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission. | 06-25-2009 |
| 20090161298 | HYBRID CAPACITOR - A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer. | 06-25-2009 |
| 20110157775 | DECOUPLING DEVICE - A decoupling device includes a lead frame, a capacitor unit, a metal layer, and a high dielectric organic-inorganic composite material layer. The lead frame includes a cathode terminal portion and an anode terminal portion. The capacitor unit is disposed on the lead frame. The capacitor unit includes a cathode portion, an anode portion, and an insulation portion located between the cathode portion and the anode portion. The cathode portion is electrically connected to the cathode terminal portion, and the anode portion is electrically connected to the anode terminal portion. The high dielectric organic-inorganic composite material layer is connected to the capacitor unit in parallel via the metal layer. | 06-30-2011 |
Chia-Ming Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110128354 | SYSTEM AND METHOD FOR OBTAINING CAMERA PARAMETERS FROM MULTIPLE IMAGES AND COMPUTER PROGRAM PRODUCTS THEREOF - Systems and methods for obtaining camera parameters from images are provided. First, a sequence of original images associated with a target object under circular motion is obtained. Then, a background image and a foreground image corresponding to the target object within each original image are segmented. Next, shadow detection is performed for the target object within each original image. A first threshold and a second threshold are respectively determined according to the corresponding background and foreground images. Each original image, the corresponding background image, the first and second threshold are used for obtaining silhouette data and feature information associated with the target object within each original image. At least one camera parameter is obtained based on the entire feature information and the geometry of circular motion. | 06-02-2011 |
Chia-Yun Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090214136 | IMAGE PROCESSING APPARATUS FOR SCALING AN INPUT IMAGE ACCORDING TO VARIOUS IMAGE PROCESSING REQUIREMENTS AND METHOD THEREOF - An image processing apparatus and method for scaling an input image are disclosed. The image processing apparatus includes a buffer module, a scaling unit, and a determining unit. The buffer module includes at least a line buffer for buffering pixel data of the input image. The scaling unit is coupled to the buffer module and includes a plurality of filters having different filter tap numbers, wherein the scaling unit utilizes a target filter having a specific filter tap number selected from the plurality of filters to scale the input image according to the pixel data retrieved from the line buffer. The determining unit is coupled to the scaling unit and utilized for receiving an image processing requirement and setting a pixel precision of the input image and selecting the target filter having the specific filter tap number from the filters in the scaling unit according to the image processing requirement. | 08-27-2009 |
| 20090316775 | VIDEO ENCODING AND DECODING METHOD AND SYSTEM THEREOF - A video encoding system for encoding at least one frame, which includes a plurality of data units, to a bit stream. The system includes: a scaling unit, for scaling a data unit of a current frame to generate a scaled data unit in a first mode; and a video encoder, coupled to the scaling unit, for directly retrieving the scaled data unit from the scaling unit and encoding the scaled data unit to generate a coded data unit in the first mode. | 12-24-2009 |
| 20100027973 | IMAGE PROCESSING CIRCUIT AND METHOD CAPABLE OF PERFORMING ONLINE COLOR SPACE CONVERSION - An image processing circuit includes: a video decoder for decoding at least one block image source to generate first decoded data, where the block image source and the first decoded data correspond to a first color space; a color space converting unit, coupled to the video decoder, for performing color space conversion on the first decoded data to generate second decoded data, where the second decoded data corresponds to a second color space; a block based scaling unit, coupled to the color space converting unit, for performing a scaling operation on the second decoded data to generate scaled data, where the scaled data corresponds to the second color space; and a frame buffer, coupled to the block based scaling unit, for temporarily storing the scaled data, where the scaled data temporarily stored in the frame buffer is utilized in the second color space. | 02-04-2010 |
| 20100034288 | VIDEO DECODING METHOD AND SYSTEM THEREOF - A video decoding method for decoding a bit stream to a plurality of frames, includes: determining whether a size of a current picture is equal to that of a next picture according to the bit stream; scaling a corresponding reference frame for the next picture to generate a scaled frame when the size of the current picture is not equal to that of the next picture; and storing the scaled frame in a first frame buffer of a storage unit, wherein at least a portion of a first frame originally stored in the first frame buffer is displayed. | 02-11-2010 |
Chieh-Wen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100259233 | Direct Current Converter - A direct current converter includes a first node, a second node, an input voltage terminal, an output voltage terminal, a bootstrap source terminal, a low-voltage terminal, a control module for generating a control signal, a driving-stage circuit coupled to the input voltage terminal, the first node, the second node, the control module, and the low-voltage terminal, an output-stage circuit coupled to the second node and the output voltage terminal, and a bootstrap circuit including a capacitor coupled between the first node and the second node, a fault detector for outputting a switch signal, and a cascade unit coupled to the bootstrap source terminal, the first node, the control module, and the fault detector for controlling connection between the bootstrap source terminal and the first node according to the switch signal and the control signal. | 10-14-2010 |
| 20100259238 | Direct Current Converter - A direct current converter includes a first node, a second node, an input voltage terminal end, an output voltage terminal, a control power terminal, a low-voltage end, a control module for generating a control signal, a driving-stage circuit coupled to the input voltage terminal, the first node, the second node, the control module, and the low-voltage end, an output-stage circuit coupled to the second node and the output voltage terminal, and a bootstrap circuit including a capacitor coupled between the first node and the second node, and a cascade unit coupled to the control power terminal, the first node, and the control module for controlling connection between the control power terminal and the first node according to the control signal. | 10-14-2010 |
| 20110043178 | Electronic Device with Power Switch Capable of Regulating Power Dissipation - An electronic device with a power switch capable of regulating power dissipation includes a power supply device; a power switch, for providing an output voltage; and a current regulating circuit, which includes an adaptive control unit, for outputting a regulating signal, according to the voltage difference between the power supply device and the output voltage; and a switch control unit, for outputting a switch control signal to control the magnitude of the current through the power switch, according to the regulating signal. | 02-24-2011 |
Chien-Hong Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110198571 | ORGANIC COMPOUND AND ORGANIC ELECTROLUMINESCENCE DEVICE EMPLOYING THE SAME - Organic compounds and organic electroluminescence devices employing the same are provided. The organic compound has a chemical structure represented as follows: | 08-18-2011 |
Chi-Feng Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080265256 | MOS devices with improved source/drain regions with SiGe - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage. | 10-30-2008 |
Chin Chung Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100060190 | LIGHT-EMITTING DIODE DRIVING CIRCUIT - A light-emitting diode driving circuit includes an AC/DC converting circuit for converting an AC power source into a DC power source; a switching element having an input contact connected to the AC/DC converting circuit; a control unit for outputting a control signal to the switching element at a set frequency to turn on or turn off the switching element, wherein a first resistor is disposed between a power contact thereof and the input contact of the switching element; a second resistor for enabling the control unit to detect a half-cycle voltage of the DC power source; a capacitor having a first end connected to the power contact, and a second end connected to a ground contact of the control unit; and an inductor having a first end connected to the ground contact and the second end of the capacitor, and a second end connected to a light-emitting diode. | 03-11-2010 |
| 20110012522 | FIXED FREQUENCY DIMMING METHOD AND FIXED FREQUENCY DIMMING CIRCUIT FOR LIGHT EMITTING MODULE - A fixed frequency dimming method and fixed frequency dimming circuit for a light emitting module can control light emitting brightness of the light emitting module through a hysteresis control circuit. A voltage difference between an upper limit voltage and a lower limit voltage of a hysteresis width of the hysteresis control circuit is maintained at a fixed value, and a driving current flowing through the light emitting module is changed by changing the upper limit voltage or the lower limit voltage. | 01-20-2011 |
Ching-Tai Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080303157 | HIGH THERMAL CONDUCTIVITY SUBSTRATE FOR A SEMICONDUCTOR DEVICE - A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and digital signal processors (DSPs). For some embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower cavity with one or more metal layers deposited therein to dissipate heat away from the semiconductor dies. For other embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower surface with one or more metal layers deposited thereon for efficient heat dissipation. | 12-11-2008 |
| 20110111537 | HIGH THERMAL CONDUCTIVITY SUBSTRATE FOR A SEMICONDUCTOR DEVICE - A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and digital signal processors (DSPs). For some embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower cavity with one or more metal layers deposited therein to dissipate heat away from the semiconductor dies. For other embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower surface with one or more metal layers deposited thereon for efficient heat dissipation. | 05-12-2011 |
Ching-Yuan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090167944 | Video-signal receiving apparatus and method - A video-signal receiving method is provided. First, receive an analog video signal, wherein the analog video signal comprises a specific video signal and a synchronization signal. Next, at least perform an analog-to-digital conversion on the synchronization signal of the analog video signal according to a sampling signal to generate a digital signal. Then, receive the digital signal and decoding the digital signal to obtain a digital synchronization signal corresponding to the synchronization signal. Afterward, adjust a phase of the sampling signal according to the digital synchronization signal. | 07-02-2009 |
Chin-Wen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080201509 | Component, device and operation method for digital data integration - A component, device and operation method for digital data integration solves the shortcoming of the prior art that playing audio recordings and reading/writing AV data cannot be performed simultaneously. The digital data integration device receives a start signal from a computer to enable a plurality of endpoints declared in a program memory unit of the digital data integration component. The present invention utilizes a bulk mode for audio input/output endpoint to play/record audio data and a bulk mode for mass-storage read/write endpoint to upload/download digital data through a control endpoint combination with an interrupt read endpoint and an interrupt write endpoint. The present invention can play/record sound data and upload/download digital data simultaneously. | 08-21-2008 |
Chuan-Te Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100290224 | DUAL LAMP ILLUMINATION SYSTEM AND ITS VARIFOCAL LIGHT-MIXING DEVICE - A dual lamp illumination system includes a first light source, a second light source, a light-deflecting device, a light-homogenizing device, and a lens assembly. The light-deflecting device is positioned in both a first light path of the first light beam and a second light path of the second light beam to combine the first light beam with the second light beam. The lens assembly includes a first set of varifocal lenses neighboring the light-deflecting device and a second set of varifocal lenses neighboring the light-homogenizing device. The composition of the first set of varifocal lenses is identical to the composition of the second set of varifocal lenses, and the first set of varifocal lenses and the second set of varifocal lenses are positioned substantially in symmetry. | 11-18-2010 |
Chun-Hu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100317184 | METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material. | 12-16-2010 |
Chun-Yuan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090128783 | Ocular-protection projector device - The present invention discloses an ocular-protection projector device, wherein the projector is additionally equipped with an image-capture unit. When the projector projects information onto a screen, the image-capture unit captures the human-shape image of a user. An image-processing unit, which is arranged inside the projector or an external electronic device, receives the human-shape image, creates a human-shape black mask, and outputs the human-shape black mask via the projector onto an area of the screen corresponding to the user's position. Thereby, the present invention can effectively protect the user's eyes from the harm of intense light. | 05-21-2009 |
Hao-Ying Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080240500 | IMAGE PROCESSING METHODS - A method of image processing, the method comprising receiving an image frame including a plurality of pixels, each of the plurality of pixels including an image information, conducting a first extraction based on the image information to identify foreground pixels related to a foreground object in the image frame and background pixels related to a background of the image frame, scanning the image frame in regions, identifying whether each of the regions includes a sufficient number of foreground pixels, identifying whether each of regions including a sufficient number of foreground pixels includes a foreground object, clustering regions including a foreground object into at least one group, each of the at least one group corresponding to a different foreground object in the image frame, and conducting a second extraction for each of at least one group to identify whether a foreground pixel in the each of the at least one group is to be converted to a background pixel. | 10-02-2008 |
Hong-Chen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080258813 | Sense Amplifiers Operated Under Hamming Distance Methodology - A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs. | 10-23-2008 |
| 20090290446 | Memory Word-line Tracking Scheme - A word-line tracking system for a memory array having a plurality of memory cells, the word-line tracking system comprises a dummy row having substantially identical structure as one or more regular rows of the memory cells, the dummy row including a dummy word-line having a first and a second end at the opposite longitudinal ends of the dummy word-line, the first end being connected to a word-line driver, a self timing generator configured to receive a clock signal and generate a pulse signal in sync with the clock signal for the dummy word-line driver, the self timing generator having a first terminal for receiving a feedback signal to determine the falling edge of the pulse signal, a voltage-to-current converter connected to the second end of the dummy word-line, a current-to-voltage converter connected to the feedback terminal, and a wire connecting the voltage-to-current converter to the current-to-voltage converter. | 11-26-2009 |
| 20110158007 | MULTI-POWER DOMAIN DESIGN - In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA. | 06-30-2011 |
| 20110188326 | DUAL RAIL STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control. | 08-04-2011 |
| 20110194362 | WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT - A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array. | 08-11-2011 |
Hsien-Chie Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090184393 | MEMORY CAPACITOR AND MANUFACTURING METHOD THEREOF - The structure strength of a memory capacitor is reduced as the height of the memory capacitor is increased, which results in collapse and a short circuit. This invention provides a capacitor with a special reinforced structure outside, wherein the reinforced structure extends upward from the bottom of the lower electrode of the capacitor to a height, thus reducing the deformation caused by the process loading and supplying sufficient capacitance. In addition, the height of the reinforced structure is adaptable to requirement. Thereby, even when the capacitors are connected with one another because the capacitors collapse, the capacitors are prevented from malfunction. Moreover, the reinforced structures can be connected to one another or not, and thus the structure strength of the capacitor arrays is increased. Besides, the process is simplified and the cost is also reduced. | 07-23-2009 |
| 20090257169 | STACKED CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF - In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space. | 10-15-2009 |
Hsin-An Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080284963 | Liquid crystal panel for liquid crystal display device - To utilize effectively the panel space of the liquid crystal panel, this invention has provided a wiring structure, in which the seal material and BM are coated in a superposition and the UV light is irradiated from one side of the TFT substrate; this invention has also provided a wiring structure, in which the seal material can still be irradiated by the UV light with high efficiency, meanwhile, the drop of the resistance value of the metal wiring on the TFT substrate can be restricted to a specific range. The solution is: the liquid crystal dropped is sandwiched between the TFT substrate and the CF substrate, meanwhile the liquid crystal panel is formed by adhering the light cured seal material disposed at the peripheral area of two substrates. In the adhering-formed liquid crystal panel, for the wiring portion, which is the portion of wiring disposed on the TFT substrate superposing the light cured seal material, the wiring structure is formed as follows, that is, the region of the seal material is divided into three regions, an adjacent region, a middle region and an outer region. The function of the respective regions must be held, and the resistance of the metal wiring is minimized under the precondition that the respective function is satisfied sufficiently. | 11-20-2008 |
Hsiu-Yu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100270238 | METHOD FOR TRANSFERRING INORGANIC OXIDE NANOPARTICLES FROM AQUEOUS PHASE TO ORGANIC PHASE - A method for transferring inorganic oxide nanoparticles from aqueous phase to organic phase. A modifier is used to change the surface polarity of inorganic oxide nanoparticles, followed by using proper solvents to transfer the modified inorganic oxide nanoparticles form aqueous phase to organic phase. The organic dispersion of modified inorganic oxide nanoparticles can be combined with a polymer to provide a polymer composite with the nanoparticles uniformly dispersed therein. | 10-28-2010 |
Hsu-Chen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080291720 | SPIN TORQUE TRANSFER MRAM DEVICE - The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area. | 11-27-2008 |
| 20090290410 | SPIN TORQUE TRANSFER MRAM DEVICE - The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area. | 11-26-2009 |
| 20100118603 | DEVICE AND METHOD OF PROGRAMMING A MAGNETIC MEMORY ELEMENT - The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction. The first and second currents cause the non-fixed magnetization of the second magnetic element to toggle between substantially parallel to the fixed magnetization of the first magnetic element and between substantially antiparallel to the fixed magnetization of the first magnetic element. | 05-13-2010 |
Huai Yu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090250816 | ULTRA-THIN DIFFUSION-BARRIER LAYER FOR CU METALLIZATION - Diffusion barrier layer is required during copper metallization in IC processing to prevent Cu from diffusion into the contacting silicon material and reacting to form copper silicide, which consumes Cu and deteriorates electrical conduction. With decreasing feature sizes of IC devices, such as those smaller than 90 nano-meter (nm), the thickness of diffusion barrier layer must be thinner than 10 nm. For example, a thickness of 2 nm will be called for at the feature size 27 nm. Disclosed in the present invention is ultra-thin barrier materials and structures based on tantalum silicon carbide, and its composite with another metallic layer Ru film. The retarding temperature, by which no evidence of copper diffusion can be identified, is 600˜850° C. depending on thickness, composition and film structure, at a thickness 1.6˜5 nm. | 10-08-2009 |
Huang-Chung Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100133544 | THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF - A thin film transistor (TFT) includes a poly-silicon island, a gate insulating layer, a gate stack layer, and a dielectric layer. The poly-silicon island includes a source region and a drain region. The gate insulating layer covers the poly-silicon island. The gate stack layer is disposed on the gate insulating layer and includes a first conductive layer and a second conductive layer. A length of the first conductive layer is less than a length of the second conductive layer. The dielectric layer covers the gate insulating layer and the gate stack layer, and therefore a number of cavities are formed between the second conductive layer and the gate insulating layer. | 06-03-2010 |
| 20100258808 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor and a manufacturing method thereof are provided. A bottom gate, a gate insulating layer and an amorphous semiconductor layer are formed on a substrate. The amorphous semiconductor layer has an uneven upper surface. A laser annealing process is performed on the amorphous semiconductor layer through the uneven upper layer to transform the amorphous semiconductor layer into a polycrystalline semiconductor layer having a smaller-crystallizing-section and a greater-crystallizing-section. Another gate insulating layer, an upper gate and patterned photoresist layer are formed on the polycrystalline semiconductor layer. Patterns of the upper gate and the bottom gate are defined by the same photo-mask. A source/drain is formed in the polycrystalline semiconductor layer. An etching process with etching selectivity is performed on the upper gate and the patterned photoresist layer to make a length of the upper gate shorter than that of the bottom gate. | 10-14-2010 |
| 20110084283 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor and a manufacturing method thereof are provided. An insulating pattern layer having at least one protrusion is formed on a substrate. Afterwards, at least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. Later, the spacer and the amorphous semiconductor patterns are crystallized. Subsequently, the protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. Then, a carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer. | 04-14-2011 |
Hui Wen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100275335 | SCANNING PROBE AND METHOD FOR ATTACHING CONDUCTIVE PARTICLE TO THE APEX OF THE PROBE TIP OF THE SCANNING PROBE - A method for attaching a conductive particle to the apex of a probe tip comprises the steps of: moving the apex of a probe tip close to a conductive particle and applying a bias voltage between the probe tip and the conductive particle so that the conductive particle can permanently attach to the apex. The method uses only a bias voltage to transfer and attach conductive particles to the apex of a probe tip, and no surface treatment of the probe tip is required. | 10-28-2010 |
Hung-Chiao Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090038547 | AUTOMATIC WAXING APPARATUS AND METHOD - An automatic waxing apparatus and a method thereof are provided. The automatic waxing apparatus includes a movable door-shaped module, at least a waxing module and a controlling module. The movable door-shaped module includes a door-shaped structure capable of moving with respect to the vehicle. The waxing module disposed on the door-shaped structure includes a wax-supplying unit and a wax-polishing unit. The controlling module is coupled to the door-shaped structure, the wax-supplying unit and the wax-polishing unit. The controlling module, according to the information of the vehicle, determines a moving path of the door-shaped structure, a waxing path of the wax-supplying unit, and a polishing path of the wax-polishing unit with respect to the vehicle. | 02-12-2009 |
| 20090105112 | Nono-clay composite and composition for fabricating the same - The present invention relates to a nano-clay composite and a composition for fabricating the same. The nano-clay composite of the invention is formed by compounding a composition comprising a polymer, a surfactant, a polymer modification component, and micro/nano powders. The nano-clay composite is flexible to completely adhere to cleaning surfaces to remove unwanted materials via the release of surfactant, as well as the scrubbing effect produced by the friction between micro/nano powders and the surface. | 04-23-2009 |
| 20090117794 | Composition for forming antifogging coating and fabric textile applying the same method of forming the antifogging coating - A composition for forming an antifogging coating is provided. The composition includes substantially 0.1 to 10 parts by weight of numerous ultrafine particles, substantially 0.1 to 10 parts by weight of a polymeric electrolyte and substantially 80 to 100 parts by weight of water. When a layer of the composition on a material surface is dried, the antifogging coating of super-hydrophilic nanostructure constructed by these ultrafine particles is formed on the material surface. | 05-07-2009 |
| 20100151776 | Polishing body and device for removing stain - A polishing body for removing stains is provided. The polishing body includes a fiber material or a fabric and a concave is formed in the polishing body to achieve the effects of slowly releasing polishing agent and effort-saving. | 06-17-2010 |
| 20100317780 | Removable Hydrophobic Composition, Removable Hydrophobic Coating Layer and Fabrication Method Thereof - A removable hydrophobic composition, a removable hydrophobic coating layer and a fabrication method thereof are provided. The removable hydrophobic composition comprises 0.1-50 parts by weight of nano-particles having diameters smaller than 100 nm and of which surfaces are modified with silicon hydride compound, 0.1-5 parts by weight of an adhesion regulator or adhesion inhibitor, 100 parts by weight of a solvent, and 0.1-50 parts by weight of a polymer compound. | 12-16-2010 |
Jing-Yuan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080278242 | Amplifier - An amplifier has a self-bias circuit to generate the bias voltage for the input of the amplifying circuit in the amplifier, thereby simplifying the circuit complexity to reduce the size and cost of the amplifier. | 11-13-2008 |
Jui-Chung Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090174927 | Method and Apparatus for Manufacturing Electrophoretic Displays - A method for manufacturing an electrophoretic display includes the steps of: providing a substrate; forming a flexible plate on the substrate; forming an electrophoretic layer on the flexible plate; forming a transparent protection layer on the electrophoretic layer; forming an edge protection member between the flexible plate and the transparent protection member, the edge protection member surrounding the electrophoretic layer; and providing a laser beam to irradiate the flexible plate from a side of the substrate facing away from flexible plate, so as to release the substrate from the flexible plate. | 07-09-2009 |
| 20090230280 | Carrier and Method for Manufacturing Flexible Display Panel - A carrier applicable to a laser releasing process and for carrying at least a flexible display panel is provided. The flexible display panel is formed on a transparent substrate and includes a display main body and a driving circuit module connected to an edge of the display main body. The carrier includes a carrying plate having at least a carrying area for carrying the flexible display panel and a protecting cover disposed on the carrying plate and located at an edge of the carrying area. A receiving space is formed between the protecting cover and the carrying plate for receiving the driving circuit module. The protecting cover is for shielding the driving circuit module to prevent the driving circuit module from being irradiated by a laser beam in the laser releasing process. A method for manufacturing flexible display panel also is provided. | 09-17-2009 |
Kong-Wei Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100151153 | METHOD AND APPARATUS FOR GROWING A COMPOSITE METAL SULPHIDE PHOTOCATALYST THIN FILM - A method and apparatus are provided for growing a composite metal sulphide photcatalyst thin film, wherein photochemical deposition and chemical bath deposition are both performed for growing the composite metal sulphide thin film, such as (AgInS | 06-17-2010 |
Kung-Yu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100164369 | APPARATUS OF ORGANIC LIGHT EMITTING DIODE AND PACKAGING METHOD OF THE SAME - A packaging method of an organic light emitting diode (OLED) is described. First, a substrate is provided, and the substrate has the OLED device formed thereon. Thereafter, at least one protection layer is formed on the substrate, so as to cover the peripheral sidewall of the OLED device entirely. The step of forming the protection layer includes forming an organic layer on the substrate, and then forming a metal layer on the organic layer, wherein the metal layer at least covers a sidewall of the OLED device. Afterwards, an oxidation treatment is performed, so as to oxidize a portion of the metal layer. | 07-01-2010 |
Li-Ju Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110097617 | Battery Set with Heat Conducting Jelly - A battery set filled with heat conducting jelly is disclosed, which comprises a shell, for housing a cooling unit; and a plurality of battery cells, each battery cell being disposed inside the shell while having a heat conducting jelly, featuring with electric insulation and heat conduction abilities, to be filled surrounding the periphery thereof and contacting with the outer surface of each battery cell. | 04-28-2011 |
Li-Wei Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090242997 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 10-01-2009 |
| 20110031558 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE - A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer. | 02-10-2011 |
| 20110034019 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 02-10-2011 |
Long-Cheng Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090016551 | ELECTROSTATIC ELECTROACOUSTIC TRANSDUCERS - An electrostatic electroacoustic device comprising a first electrode configured to receive an audio signal, a second electrode configured to receive the audio signal, a first electret between the first electrode and the second electrode, the first electret including at least one dielectric layer containing electrostatic charges, a second electret between the first electrode and the second electrode, the second electret including at least one dielectric layer containing electrostatic charges, and a conductive layer sandwiched between the first electret and the second electret, the conductive layer, the first electret and the second electret being capable of vibratory motion relative to the first electrode and the second electrode based on the audio signal. | 01-15-2009 |
Ming-Hsin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090221144 | Manufacturing method for nano scale Ge metal structure - Manufacturing methods for nano scale Ge include: Form dielectric layer on the substrate surface, then etch the dielectric layer to form openings of three different dimensions, then use chemical vapor deposition process to deposit Ge metal layer to cover the substrate, dielectric layer and the openings; then on the opening of three different dimensions, nano-dot, nano-disk and nano-ring are formed. | 09-03-2009 |
| 20100216298 | Method for growing Ge expitaxial layer on patterned structure with cyclic annealing - A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device. | 08-26-2010 |
Ming-Jen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090042894 | NOVEL SPECIES OF ACROCARPOSPORA, A METHOD OF PREPARING IODININ, AND THE USES OF IODININ - The present invention provides a novel species of | 02-12-2009 |
| 20110165186 | NOVEL PYRIDINE ALKALOIDS, PREPARATION PROCESS THEREOF, AND THE USES OF THE PYRIDINE ALKALOIDS - The present invention relates to novel pyridine alkaloid compounds of formula (I): | 07-07-2011 |
Nai-Han Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100221849 | METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS - A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD. | 09-02-2010 |
Nai-Sheng Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090131176 | GAME PROCESSING DEVICE - A game processing device in a displaying apparatus is capable of receiving a game data from an electronic device outside the displaying apparatus. The game processing device comprises: a transmission interface module, for receiving a game data, wherein the game data is used for rendering at least one game image; and a processing module, coupled to the transmission interface module, for rendering the game image according to the game data. | 05-21-2009 |
Pi-Ying Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080271528 | SENSING DEVICE - The present invention discloses a sensing device, wherein a hemispherical container containing a liquid dielectric, and the hemispherical container has more than two pairs of electrodes, and the liquid dielectric can trigger the conduction states of the electrodes. A corrosion-resistant material envelops the container. A precision valve is arranged in the container and used to adjust the level of the liquid dielectric and the sensitivity of the sensing device. A buffer necking part is also arranged in the container and used to prevent from non-expected vibration-induced contact between the electrodes and the liquid dielectric. A leakage-proof detection device envelops the hemispherical container, the liquid dielectric, the precision valve, and the buffer necking part and functions to prevent from the leakage of the liquid dielectric. Thus, the present invention can provide an adjustable multi-directional tilt-sensing device for level control. | 11-06-2008 |
Po-Tai Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110080157 | FLUX LINKAGE COMPENSATOR FOR UNINTERRUPTIBLE POWER SUPPLY - The present invention discloses a flux linkage compensator, which applies to an UPS system and comprises a load transformer flux linkage observer, a compensation voltage command generator, and a flux linkage command generator. The load transformer flux linkage observer generates a load transformer flux linkage signal. The flux linkage command generator generates a flux linkage command signal. The difference between the load transformer flux linkage signal and the flux linkage command signal forms a flux linkage deviation signal. The compensation voltage command generator generates a voltage compensation signal to make the flux linkage deviation signal approach zero. Thereby, the flux linkage compensator can compensate for the flux linkage deviation occurring in starting the UPS system. Thus, the present invention can perform voltage compensation fast and reliably and inhibit the inrush current effectively. | 04-07-2011 |
Po-Wen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100315269 | Decoding Method - A decoding method comprising the following steps is provided. The m | 12-16-2010 |
Terry Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100212100 | Cleaning Apparatus for Sophisticated Electric Device - A cleaning apparatus is provided to clean a sophisticated electric device. The apparatus has cleaning units and each of the cleaning units has a cambered top. Thus, coordinated with an actuating device, a sophisticated electric device can be cleaned by using the cleaning apparatus with cleaning units having cambered tops. | 08-26-2010 |
Tsung-Chieh Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100216298 | Method for growing Ge expitaxial layer on patterned structure with cyclic annealing - A Ge epitaxial layer is grown on a silicon substrate with a patterned structure. Through a cyclic annealing, dislocation defects are confined. The present invention provides a method for manufacturing a high-quality Ge epitaxial layer with a low cost and a simple procedure. The Ge epitaxial layer obtained can be applied to high mobility Ge devices or any lattice-mismatched epitaxy on a photonics device. | 08-26-2010 |
Tun-Jen Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090039425 | HIGH-VOLTAGE MOS TRANSISTOR DEVICE - A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device. | 02-12-2009 |
Wei-Kai Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110018819 | Touch Panel Interface System Used on Touch Panel, Touch device, and Method thereof - For solving the defect that a hardware clock of a serial peripheral interface bus has to cooperate with slower software-simulated clocks used by a microprocessor while applying serial peripheral interface buses on a large-scale touch panel, a programmable logic device is used as a bridge of communicating information between the micro processor and sensors. Therefore, the microprocessor no longer has to take execution time to simulate serial peripheral interface buses by software, and is able to program hardware clocks of each of the serial peripheral interface buses according to speed requirements of different sensors, so that sensing signals of a plurality of sensors may be integrated on a touch device having the large-scale touch panel, and a processing speed of the touch device in processing the sensing signals may be optimized as a result. | 01-27-2011 |
| 20110025641 | TOUCH SCREEN APPLIED TO ELECTRONIC APPARATUS - A touch screen includes a substrate, a plurality of conductive areas and a controller. The conductive areas are disposed on the substrate. The controller is electrically connected to the conductive areas. When one of the conductive areas is touched, the controller determines a coordinate where the touched conductive area is located on the substrate according to the capacitance change of the touched conductive area. | 02-03-2011 |
Wen-Cheng Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100051581 | PLASMA CLEANING FOR PROCESS CHAMBER COMPONENT REFURBISHMENT - A method for cleaning and refurbishing a chamber component includes placing a chamber component having process deposits on an exterior surface in a plasma vapor deposition chamber. The chamber component is bombarded with a plasma comprising Argon for a period of time sufficient to remove the process deposits from the exterior surface of the chamber component. | 03-04-2010 |
Wen-Chin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110100556 | Plasma System with Injection Device - A plasma system with an injection device is provided. The plasma system comprises a plasma cavity and an injection device. The plasma cavity comprises a first electrode and a second for generating plasma. The injection device comprises a plasma injection tube and at least a reactant injection tube. The plasma injection tube is connected to the plasma cavity. The plasma injection tube comprises an inlet, an outlet and an outer sidewall. The plasma injection tube injects the plasma from the inlet and guides the plasma out through the outlet. The outer sidewall has a width decreasing from the inlet to the outlet. The reactant injection tube is disposed outside of the outer sidewall. The reactant injection tube injects a reactant to the outer sidewall so that the reactant flows along the outer sidewall toward the outlet and mixes with the plasma at the outlet. | 05-05-2011 |
Wenchu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100241414 | DEBUGGING SIMULATION WITH PARTIAL DESIGN REPLAY - A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models. Each executed replay engine simulates behavior of each output signal of a corresponding low-level module in response to the data recorded during the initial simulation representing the behavior of that output signal. | 09-23-2010 |
Wen-Fang Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080201451 | SYSTEMS AND METHODS FOR REAL-TIME MEDIA COMMUNICATIONS - A system for real-time media communication comprises a first server unit configured to interface between at least one user and a blog and a second server unit configured to process the real-time media content in a streaming mode. The first server unit comprises a publishing control module configured to identify an identity of a publisher of the at least one user, allow the publisher to transmit real-time media content if the identity of the publisher is authentic and receive a description of the real-time media content from the publisher, and a link module configured to obtain a location of the real-time media content so that the location of the real-time media content is accessible to the at least one user. The second server unit comprises a receiving module configured to receive the real-time media content, a recording module configured to record the real-time media content, and a dispatching module configured to provide the location of the real-time media content to the publishing module. | 08-21-2008 |
Wen-Hsin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100271294 | Method for Reducing Resonance Energy of an LCD panel and Related LCD Device - A method for reducing resonance energy of an LCD panel includes providing a plurality of driving signal patterns, each defining a non-overlap area width of a synchronization signal and a scan-line charging frequency, and determining an order of the plurality of driving signal patterns to modulate driving signals of the LCD panel accordingly. | 10-28-2010 |
William Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080296571 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 12-04-2008 |
| 20110006404 | STRUCTURE AND METHOD OF WAFER LEVEL CHIP MOLDED PACKAGING - A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages. | 01-13-2011 |
Yao-Chin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090117701 | METHOD FOR MANUFACTURING A MOS TRANSISTOR - A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility. | 05-07-2009 |
| 20090186475 | Method of manufacturing a MOS transistor - A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided. | 07-23-2009 |
| 20090246922 | METHOD OF FORMING CMOS TRANSISTOR - A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again. | 10-01-2009 |
Yen-Chien Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110055857 | MOVE-SLED-HOME DEVICE AND METHOD FOR USE IN OPTICAL DISC DRIVE - A move-sled-home device is used in an optical disc drive. The move-sled-home device includes a processing unit, a motor actuator, a sled, a sled motor, and a current-detecting unit. The processing unit outputs a control signal. The motor actuator generates a driving voltage according to the control signal. The sled motor generates a driving current according to the driving voltage to move the sled. The current-detecting unit is used for receiving and converting the driving current into an indicating signal, and issuing the indicating signal to the processing unit. During a move-sled-home action, the processing unit realizes a magnitude of the driving current according to the indicating signal, thereby determining whether the move-sled-home action is finished. | 03-03-2011 |
| 20110158614 | MOTOR ROTATION SPEED CONTROL DEVICE AND METHOD THEREOF - A motor rotational speed control device for controlling a direct current (DC) brush motor is provided, which includes a motor driver, a detection unit and a central processing unit (CPU). The motor driver is coupled to a first control terminal and a second control terminal of the DC brush motor. The detection unit detects a back electromotive force (EMF) of the DC brush motor through the first control terminal and the second control terminal when the motor driver is set to a disable state, and accordingly generates back EMF information. The CPU determines whether the direct current brush motor has stopped rotating according to the back EMF information, and determines whether to generate a brake control signal according to a determination result. The motor driver reduces a rotation speed of the DC brush motor according to the brake control signal when the motor driver is set to an enable state. | 06-30-2011 |
Ying-Chuan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110141099 | DRIVING METHOD FOR PIXELS OF BISTABLE DISPLAY - A driving method for pixels of bistable display is adapted into a bistable display having a plurality of pixels. The driving method comprises: increasing predetermined driving forces of the pixels to increased driving forces in a predetermined period; employing the increased driving forces to drive the pixels in the predetermined period respectively; and employing the predetermined driving forces configured for driving the pixels to drive the pixels out of the predetermined period respectively. | 06-16-2011 |
Yi-Shan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090118231 | Pectin-modified resistant starch, a composition containing the same and method for preparing resistant starch - This invention relates to a pectin-modified resistant starch prepared by cross-linking starch with pectin by pectinesterase reaction. Such resistant starch is low amylase digestible and thus is useful in food products, including nutritional supplements, to reduce calorie content and increase fiber content. This invention also relates to a composition containing the resistant starch and a process for the preparation of the same. | 05-07-2009 |
Yu Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090212868 | LOW POWER COMSUMPTION, LOW NOISE AND HIGH POWER GAIN DISTRIBUTED AMPLIFERS FOR COMMUNICATION SYSTEMS - Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed. | 08-27-2009 |
Yuh Chuan Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100142754 | INSPECTION METHOD AND SYSTEM FOR DISPLAY - A ghost image inspection system comprises a carrier, a reflectance measurement apparatus, and a processing apparatus. The carrier is configured to support the electronic paper display, and the electronic paper display is configured to show a test pattern and at least one sub-frame. The test pattern has a plurality of optical states. The reflectance measurement apparatus is coupled to the carrier and is configured to measure reflectances of the test pattern and at least one sub-frame, and the processing apparatus is coupled to the reflectance measurement apparatus and is configured to determine whether the reflectance is worse than a threshold value of a ghost image index. | 06-10-2010 |
Yu Hsain Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090018241 | HALOGEN-FREE PHOSPHOROUS EPOXY RESIN COMPOSITION - The present invention relates to a halogen-free phosphorous epoxy resin composition, primarily used as an adhesive for the printed circuit board. The composition comprises a halogen-free phosphorous contained epoxy resin which reduces the addition amount of additional flame retardant; in order to offer flame retardancy while maintaining high flexibility of flexible printed circuit board. | 01-15-2009 |
| 20100048766 | HALOGEN-FREE PHOSPHOROUS EPOXY RESIN COMPOSITION - The present invention relates to a polyphosphate-containing halogen-free adhesive, primarily used as an adhesive. The composition comprising the polyphosphate group compounds which effectively meets the needs for environmental protection and flame retardancy, and the high flexibility and flame retardancy of the adhesive made it suitable for using on printed circuit board, especially the flexible printed circuit board. | 02-25-2010 |
Yu-Lin Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090251477 | MEMORY SAVING DISPLAY DEVICE - A display device capable of saving memory storage used for an overdriving function includes a compression unit, a frame buffer, a decompression unit and a look-up table (LUT) unit. The compression unit includes a decimation filter and is used for compressing data of a received frame and reducing a size of the received frame, to generate a compression frame. The frame buffer is coupled to the compression unit and used for storing the compression frame. The decompression unit includes an interpolation filter and is used for decompressing data of the compression frame outputted by the frame buffer and reducing a size of the compression frame, to generate a decompression frame. The LUT unit is coupled to the decompression unit and used for comparing the decompression frame with a next received frame of the received frame to determine an overdriving voltage. | 10-08-2009 |
Yung-Cheng Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090256908 | INTEGRATED IMAGE SURVEILLANCE SYSTEM AND IMAGE SYNTHESIS METHOD THEREOF - Disclosed is an integrated multi-view surveillance system which integrates multiple surveillance camera images of an area into a large-coverage image of the area in order to monitor the area. The system includes a first camera, a second camera, a third camera, an image processing device, and a display device. The image processing device includes a first defining component, a first synthesis component, a second defining component, an adjusting component, a transforming component, a third defining component, and a second synthesis component. | 10-15-2009 |
Yu-Ting Cheng, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110136662 | CATALYTIC SEEDING CONTROL METHOD - A catalytic seeding control method is disclosed. A catalytic metal film is deposited on a substrate with a nonwettable inclined surface. The catalytic metal film is then melted to form metal droplets. The metal droplets roll along the nonwettable inclined surface and aggregate to form a singular catalytic seed on the bottom of the nonwettable inclined surface. Then, the location of the singular catalytic seed is precisely controlled. Also, the size of the catalytic seed is controlled by adjusting the size of the inclined surface and the thickness of the catalytic metal layer to grow a one-dimensional structure with specific localization and single well-aligned manipulated size. The structure is utilized for the integrated microelectronic device fabrication. | 06-09-2011 |