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Cheng, Hsinchu
Chia Hun Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110085353 | Frame Structure of Backlight Module - A frame structure of a backlight module includes a body and a mold frame. A side wall surrounds a bearing surface of the body, and the side wall has at least one stopper and at least one positioning hole. A side edge of the mold frame has at least one positioning post. When the mold frame is disposed on the side wall, the side edge of the mold frame leans against the stopper, and the positioning post of the mold frame is embedded in the positioning hole. | 04-14-2011 |
Chiang-Ho Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120055021 | INKJET HEAD MANUFACTURING METHOD - An inkjet head manufacturing method includes the following steps. Firstly, a multilayered structure with a plurality of microstructure layers is provided. The alignment check holes of the microstructure layers are concentric and have different diameters. Then, the microstructure layers are stacked together and the microstructure layers are aligned with each other according to the concentric and different-diameter alignment check holes, wherein a dry film layer is sandwiched between every two adjacent microstructure layers. The preset slots of the microstructure layers are collectively defined as inlet flow channels, ink chambers, pressure cavities and outlet flow channels. Then, the multilayered structure is assembled and positioned through the dry film layers by a thermal compression process. Then, a cutting knife is used to linearly cut the actuator plate over a spacer between every two adjacent pressure cavities and along a path parallel with rims of the pressure cavities. | 03-08-2012 |
| 20120062657 | PIEZOELECTRIC INKJET HEAD STRUCTURE - A piezoelectric inkjet head structure includes an upper cover plate, a lower cover plate, a piezoelectric actuating module, a nozzle plate and a seal layer. The piezoelectric actuating module includes an upper piezoelectric chip, a lower piezoelectric chip, a first electrode, a second electrode, a conductive layer and a plurality of flow channels. The entrances of the flow channels of the upper piezoelectric chip and the lower piezoelectric chip are separated from each other by the same spacing interval. The entrances of the flow channels of the upper piezoelectric chip and the entrances of the flow channels of the lower piezoelectric chip are arranged in a staggered form. During operation of the piezoelectric actuating module, ink liquid is introduced into the flow channels of the piezoelectric actuating module from the upper cover plate and the lower cover plate, and then ejected out of the nozzles. | 03-15-2012 |
Chieh Jen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110085353 | Frame Structure of Backlight Module - A frame structure of a backlight module includes a body and a mold frame. A side wall surrounds a bearing surface of the body, and the side wall has at least one stopper and at least one positioning hole. A side edge of the mold frame has at least one positioning post. When the mold frame is disposed on the side wall, the side edge of the mold frame leans against the stopper, and the positioning post of the mold frame is embedded in the positioning hole. | 04-14-2011 |
Chien-Wei Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120105351 | Touch Pad Operable with Multi-Objects and Method of Operating same - The present invention provides a touch pad operable with multi-objects and a method of operating such a touch pad. The touch pad includes a touch structure for sensing touch points of a first and a second object and a controller for generating corresponding touching signals and related position coordinates. Moreover, the controller calculates at least two movement amount indexes according to coordinate differences between these position coordinates, thereby generating a movement amount control signal to control behaviors of a software object. | 05-03-2012 |
Chi-Hao Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110168670 | Patterned Sapphire Substrate Manufacturing Method - A patterned sapphire substrate manufacturing method uses two-section dip etching procedure to improve the lateral etching rate at each etching position, so as to produce a concave-convex pattern composed of a plurality of triangular pyramid structures protruded from a surface onto an upper surface of a sapphire substrate, such that less planar area of the sapphire substrate surface will remain, and a mixed solution of sulfuric acid and phosphoric acid is used in a first dip etching step, and pure phosphoric acid or a mixed solution of sulfuric acid and phosphoric acid is used in a second dip etching step for etching the sapphire substrate to control the inclination of each triangular pyramid structure precisely, and providing a better light extraction rate for later manufactured light emitting diodes. | 07-14-2011 |
Chih-Feng Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120025860 | Burn-in socket and testing fixture using the same - A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier. | 02-02-2012 |
Ching-Yun Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110191513 | INTERRUPT CONTROL METHOD AND SYSTEM - An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit. | 08-04-2011 |
Chin Huang Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100007575 | COUPLED-LOOP CHIP ANTENNA - A loop antenna for communication is provided, which includes a microwave substrate, being a hexahedron; a first conductive layer, disposed on an upper surface of the substrate for forming a first loop; a second conductive layer, disposed on a first side surface of the substrate, and electrically connected to a feed-in point and a ground point; and a third conductive layer, disposed on a lower surface of the substrate for forming a second loop. The first conductive layer and the second conductive layer are electrically connected at the junction between the upper surface and the first side surface, and the second conductive layer and the third conductive layer are electrically connected at the junction between the first side surface and the lower surface. The antenna also has an appropriate bandwidth for wireless communication application. | 01-14-2010 |
Chiu-Hung Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080211545 | SAMPLE-AND-HOLD APPARATUS AND OPERATING METHOD THEREOF - A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively. | 09-04-2008 |
Chuan-Ho Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090067167 | BACKLIGHT STRUCTURE - A backlight structure comprises a frame, a circuit board, and a connector. The frame has an opening. The circuit board is located below the frame and has a through hole, wherein the through hole aligns with the opening. The connector passes through the opening and the through hole, protrudes from a surface of the frame, and is electrically connected to the circuit board. | 03-12-2009 |
| 20110013380 | Backlight Structure Including Clipping Connectors - A backlight structure comprises a frame, a circuit board, and a connector. The frame has an opening. The circuit board is located below the frame and has a through hole, wherein the through hole aligns with the opening. The connector passes through the opening and the through hole, protrudes from a surface of the frame, and is electrically connected to the circuit board. | 01-20-2011 |
Chun-Fai Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110024801 | TRANSISTORS HAVING A COMPOSITE STRAIN STRUCTURE, INTEGRATED CIRCUITS, AND FABRICATION METHODS THEREOF - A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate. | 02-03-2011 |
| 20110223752 | METHOD FOR FABRICATING A GATE STRUCTURE - The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode. | 09-15-2011 |
| 20110312145 | SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-22-2011 |
| 20120001238 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device. | 01-05-2012 |
| 20120056276 | STRAINED ASYMMETRIC SOURCE/DRAIN - The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes providing a substrate and forming a poly gate stack on the substrate. A dopant is implanted in the substrate at an implant angle ranging from about 10° to about 25° from perpendicular to the substrate. A spacer is formed adjacent the poly gate stack on the substrate. A source region and a drain region are etched in the substrate. A strained source layer and a strained drain layer are respectively deposited into the etched source and drain regions in the substrate, such that the source region and the drain region are asymmetric with respect to the poly gate stack. The poly gate stack is removed from the substrate and a high-k metal gate is formed using a gate-last process where the poly gate stack was removed. | 03-08-2012 |
| 20120083088 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 04-05-2012 |
Chung-Chao Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090049357 | Decoding Method for Quasi-Cyclic Low-Density Parity-Check Codes and Decoder for The Same - A decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes sequentially decodes a plurality of block codes defined by an identical parity-check matrix derived from a parity-check matrix of the QC-LDPC codes, wherein size of the identical parity-check matrix is smaller than size of the parity-check matrix. | 02-19-2009 |
Chung-Shen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100134172 | CHARGE-SHARING METHOD AND DEVICE FOR CLOCK SIGNAL GENERATION - A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low. | 06-03-2010 |
Fu-Chen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100293309 | Production Tool For Low-Level Format Of A Storage Device - A production tool for low-level format of a storage device is disclosed. The production tool includes an input connector connectable and an output connector, both of which conform to an interface standard. At least a redundant pin of the input connector is unconnected with a corresponding redundant pin of the output connector, and the redundant pin of the output connector is electrically connected to receive a provided predetermined signal, the presence of which indicating a low-level format mode. | 11-18-2010 |
His-Tsu Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110294724 | LOW HEMOLYTIC ANTIMICROBIAL PEPTIDE, PHARMACEUTICAL COMPOSITION AND USE THEREOF - Disclosed is an antimicrobial peptide having an amino acid sequence of formula presented as (P | 12-01-2011 |
His-Tsung Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100107676 | SPRAY TYPE HEAT-EXCHANGING UNIT - A spray type heat-exchanging unit includes a main body; a distributive refrigerant spray module located in an upper part of the main body and having an extended distributor and a refrigerant spray surface; and a plurality of heat exchange tubes provided in the main body below the distributive refrigerant spray module. A liquid refrigerant is guided into the extended distributor to drip onto the refrigerant spray surface, and then uniformly sprayed onto the heat exchange tubes. Gaseous refrigerant produced by evaporation in heat exchange in the main body is recovered via a top opening of the main body, making the mechanical refrigerating apparatus more efficient than a refrigerating apparatus adopting a flooded evaporator, and minimizing the refrigerant charge amount and material cost required by the heat-exchanging unit. | 05-06-2010 |
Hong-Chen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120020179 | METHOD AND APPARATUS FOR WORD LINE DECODER LAYOUT - A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines. | 01-26-2012 |
Horng-Long Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090053851 | ORGANIC THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - An organic thin film transistor array substrate including a substrate divided into an LCD region and an OTFT region; a first dielectric layer formed on the substrate in the LCD region and having a first uneven portion; an organic semiconducting layer formed on the substrate in the OTFT region; a gate, source, and drain formed in the OTFT region, wherein the source and drain are in contact with the organic semiconducting layer to form a channel between the source and drain; and a pixel electrode formed on the first uneven portion of the first dielectric layer in the LCD region. | 02-26-2009 |
Ho-Tzu Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100149426 | SYSTEMS AND METHODS FOR BANDWIDTH OPTIMIZED MOTION COMPENSATION MEMORY ACCESS - In one exemplary embodiment, methods and systems are disclosed for providing access to video data. The disclosed methods and systems comprise providing a memory device having a plurality of memory areas, and receiving a data sequence containing the video data of a plurality of blocks of a video image frame. The methods and systems also comprise storing the video data in the memory device by allocating a plurality of pixel data groups along a frame-width direction in consecutive memory-addressing areas, and allowing access to the video data in response to a data access request. | 06-17-2010 |
Hsiao-Chung Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110012891 | GATE PULSE MODULATION CIRCUIT AND LIQUID CRYSTAL DISPLAY THEREOF - The present invention relates to a gate pulse modulation (GPM) circuit and the application of same in a liquid crystal display for improving the display performance thereof. The gate pulse modulation circuit is configured to modulate multi-phase clock pulse signals so as to correspondingly generate odd gate pulse waveforms and even gate pulse waveforms that are different from one another. | 01-20-2011 |
Hsiao-Yi Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090032825 | Structure Of LED-Based Display Module And Method For Manufacturing The Same - The display module contains a circuit board, a heat-resistant and transparent protective layer, and a transparent and waterproofing enclosing member. The circuit board has a number of LED devices configured on the front surface and at least a terminal on the back surface. The LED devices are electrically and signally wired to the terminal so that electricity and video signals are fed to the LED devices via the terminal. The protective layer is coated on the outer surfaces of the LED devices and the circuit board so as to protect the wiring, the soldering contacts, and the electrical components of the circuit board from being damaged by the high temperature during the process of forming the enclosing member. The enclosing member wraps the circuit board and the LED devices entirely within and exposes only the terminal. | 02-05-2009 |
Hsin-I Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080202800 | Re-routing method and the circuit thereof - A re-routing method and the circuit thereof, used to rearrange the external circuit coupled with the integrated circuit (IC), comprises the steps of providing a plurality of first conductive plate on the substrate of the IC to form an isolation layer; providing a plurality of second conductive plates on the isolation layer, wherein each of the second conductive plates is moved in isovector with each of the corresponding first conductive plates as the center, each of the second conductive plates electrically connected with each of the first conductive plates. Therefore, according to move the second conductive plates in isovector, the probe card may be reused for circuit testing to save the cost and reduce the material management. | 08-28-2008 |
Hsiu-Yu Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120083560 | BIO-BASED MATERIAL COMPOSITION AND OPTICAL DEVICE EMPLOYING THE SAME - The invention provides a bio-based material composition and an optical device employing the same. The composition can be a petroleum resin-free composition, including a polylactic acid resin, a filler, and a light diffusion agent. Further, the composition can be a composition with petroleum resin, including a polylactic acid resin, a petroleum resin, a light diffusion agent, and an antioxidant. | 04-05-2012 |
Hsu-Chen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080239794 | Magnetoresistive random access memory device with small-angle toggle write lines - Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired. | 10-02-2008 |
| 20090085132 | MRAM Cell Structure with a Blocking Layer for Avoiding Short Circuits - A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit. | 04-02-2009 |
Hsu-Chun Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110043772 | PROJECTION MODULE AND ADJUSTMENT MECHANISM THEREOF - A projection module includes a base, a light source, a light valve, a lens module, and an adjustment module. The light source is disposed on the base and capable of providing an illumination beam. The light valve is disposed on the base and capable of converting the illumination beam into an image beam. The lens module is slidably disposed on the base and capable of projecting the image beam. The adjustment mechanism includes a rolling wheel and a slide pin. The rolling wheel is pivotably mounted to the base and includes a slide groove. The slide pin is fixed to the lens module and extends into the slide groove. The rolling wheel is capable of pivoting to drive the slide groove to pivot and the slide groove moves the slide pin to drive the lens module to move with respect to the base when the slide groove pivots. | 02-24-2011 |
Huai-Yu Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090246964 | Etching process for phase-change films - The invention is directed to a method for etching a phase change material layer comprising steps of providing a phase change material layer and performing a first etching process on the phase change material layer. The etching process is performed with an etchant comprising a fluoride-based gas with a concentration of the fluoride-based gas up to 85% of a total volume of the etchant. | 10-01-2009 |
| 20100328996 | PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions. | 12-30-2010 |
| 20110049456 | PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY - A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region. | 03-03-2011 |
| 20110097825 | Methods For Reducing Recrystallization Time for a Phase Change Material - A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer material are selected. The buffer layer material is deposited on the substrate, the phase change material is deposited on the buffer layer, and the cladding layer material is deposited on the phase change material to form a memory cell element. The thickness of the phase change material is preferably less than 30 nm and more preferably less than 10 nm. The recrystallization time of the phase change material of the memory cell element is determined. If the recrystallization time is not less than a length of time X, these steps are repeated while changing at least one of the selected materials and material thicknesses. | 04-28-2011 |
Kuang Cheng Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090195516 | Sensing Structure of a Display - A sensing structure includes a display module, a sensing unit, and a chip. The display module includes an active area. The sensing unit is disposed on the display module and overlaps at least part of the active area. The chip is disposed on the display module and outside the active area. | 08-06-2009 |
Kuan-Lun Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120119298 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°. | 05-17-2012 |
Kuo Hsing Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090059112 | Liquid Crystal Display Device, Driving Circuit, and Connection Repairing Method Thereof - A liquid crystal display device, drive circuit, and repair method thereof are provided. The drive circuit includes a plurality of signal lines and a plurality of drivers connected with the signal lines. The drivers have an ordering sequence. Each of the drivers includes a first amplifier and a second amplifier. Each of the first amplifier and the second amplifier includes an input terminal and an output terminal. The output terminal of the first amplifier of each of the driver is coupled to the input terminal of the first amplifier of the next stage driver according to the ordering sequence. The output terminal of the second amplifier of each driver is coupled to the input terminal of the second amplifier of the next stage driver according to the ordering sequence. | 03-05-2009 |
| 20090096760 | CAPACITANCE TYPE TOUCH PANEL - The present invention relates to a liquid crystal display (LCD). The LCD includes a plurality of display units formed with a first substrate, a color matrix formed on the first substrate, and a common electrode formed on the color matrix, a second substrate spaced from the first substrate, a pixel electrode matrix formed on the second substrate, a liquid crystal material disposed between the common electrode and the pixel electrode matrix. The LCD includes a touch sensing member integrated onto the color matrix of the first substrate. | 04-16-2009 |
| 20090245455 | SHIFT REGISTERS - A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal. | 10-01-2009 |
| 20090262093 | RESISTANCE TYPE TOUCH DISPLAY PANEL - A resistance type touch display panel includes a first substrate and a second substrate disposed above the first substrate. The first substrate includes many scan lines and data lines defining many pixel regions on the first substrate, many pixel units and touch units. Each pixel unit is located in one of the pixel regions and electrically connected with one of the scan lines and data lines respectively. Each touch unit is electrically connected with one of the scan lines and data lines and distributed in at least two pixel regions. The second substrate includes many spacers, many touch protrusions and a common electrode covering the spacers and the touch protrusions. Each touch protrusion is located above one of the touch units and a gap is formed between the common electrode disposed on each touch protrusion and the touch unit. | 10-22-2009 |
| 20100172461 | SHIFT REGISTERS - A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal. | 07-08-2010 |
| 20100290581 | Shift Registers - A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal. | 11-18-2010 |
| 20100328293 | Shift Register Array, and Display Apparatus - A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal. | 12-30-2010 |
Lien-Fu Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080224638 | KEY MODULE HAVING LIGHT-INDICATING FUNCTIONALITY AND A METHOD FOR CONTROLLING THE SAME - A key module includes a key, a light emitting component, and a drive circuit. The key is operable between on and off states. The light emitting component is disposed adjacent to the key, and is capable of providing indicating light for the key. The drive circuit is electrically connected to the key and the light emitting component. The drive circuit is triggered upon switching of the key from the off state to the on state to provide a drive signal with an intensity that gradually decreases over time for driving the light emitting component such that the light emitting component provides the indicating light with a luminance that gradually decreases over time. | 09-18-2008 |
| 20090046256 | PROJECTOR AND PROJECTOR CIRCUIT BOARD THEREOF - One embodiment of the invention discloses projector circuit boards comprising an image receiving terminal, a central processing unit, a motor driving module, a DMD and a DMD control module. The image receiving terminal receives an image signal and transmits the received image signal to the central processing unit. The central processing unit processes the received image signal. The motor driving module drives a motor on the basis of the processed image signal to rotate a color wheel to generate a colored beam. The DMD, comprising a plurality of micro-mirrors, is used in reflecting the colored beam, transforming the colored beam into an image beam, and transmitting the image beam to a projection lens to project an image. The rotation angles of the micro-mirrors are controlled by the DMD control module coupled between the central processing unit and the DMD. The projector circuit board is perpendicular to a light path of the projection lens. | 02-19-2009 |
Nai-Han Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080296472 | Dosage accuracy monitoring systems of implanters - An apparatus for monitoring beam currents of an implanter is provided. The apparatus includes a beam-sensing unit for sensing the beam currents; a position-determining unit for determining scan positions; and a computing unit. The computing unit is configured to perform the functions of receiving the beam currents from the beam-sensing unit; receiving the scan positions from the position-determining unit; and determining a drift status of the implanter from the beam currents, wherein the computing unit is configured to receive the beam currents and the scan position periodically between a starting time and an ending time of a scan process of the implanter. | 12-04-2008 |
Ping Chang Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080220367 | Metallocenyl Phthalocyanine Compounds and Use Thereof - This invention relates to a novel metallocenyl phthalocyanine compound represented by the following general formula (I), in which at least one of the four benzene rings of phthalocyanine is connected with the organometallic complex group through a linker having one carbon atom. This invention also relates to the use of the phthalocyanine compounds in optical recording media. | 09-11-2008 |
| 20110282052 | METALLOCENYL PHTHALOCYANINE COMPOUNDS AND USE THEREOF - This invention relates to a novel metallocenyl phthalocyanine compound represented by the following general formula (I), in which at least one of the four benzene rings of phthalocyanine is connected with the organometallic complex group through a linker having one carbon atom. This invention also relates to the use of the phthalocyanine compounds in optical recording media. | 11-17-2011 |
Pi-Ying Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100096816 | ASSISTANT APPARATUS FOR SURMOUNTING BARRIER - The present invention provides an assistant apparatus for surmounting a barrier, which comprises a carrier body, an assistant mechanism, and a sensing/driving apparatus. The assistant mechanism, disposed at a side of the carrier body, having an assistant block disposed at the end thereof, functions to place the assistant block on the ground between the carrier body and the barrier so that the carrier body is capable of surmounting the barrier through the assistance of the assistant block. The sensing/driving apparatus, coupled to the assistant mechanism, functions to drive the assistant mechanism to generate the adjusting movement according to whether the barrier is detected or not. By means of the design of the present invention, the assistant block is adopted to reduce the height surmounted by the carrier each time so that the carrier is capable of surmounting the barrier section by section. | 04-22-2010 |
Shih-Lian Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090196979 | INKJET PRINTING PROCESS FOR CIRCUIT BOARD - An inkjet printing process for a circuit board includes the following procedures. Firstly, a substrate and a conductive layer disposed on the substrate are provided. Afterward, a roughening treatment is performed on the conductive layer so that the roughness of the conductive layer is between 0.1 μm and 5 μm. Then, a patterned mask layer is printed on the conductive layer for covering an area of the conductive layer prepared for forming a circuit pattern. | 08-06-2009 |
| 20090280617 | FABRICATING PROCESS FOR SUBSTRATE WITH EMBEDDED PASSIVE COMPONENT - A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component. | 11-12-2009 |
Shih-Song Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100003507 | Multi-layer polyimide film and method of manufacturing the same - This invention relates to a multi-layer polyimide film and a method of manufacturing the same. The multi-layer polyimide film may include a functional filler. The multi-layer polyimide film is manufactured according to the method of this invention. The method includes adding tetracarboxylic acid dianhydride to a diamine solution at an equal mole ratio to form a polyamic acid solution; mixing some of the polyamic acid solution with a functional filler; adding the polyamic acid solution having the functional filler and the polyamic acid solution without the functional filler respectively to mix with aliphatic carboxylic acid anhydride and tertiary amine contained in mixing tanks to form two mixed solutions; supplying the two mixed solutions respectively to at least two reservoirs of a slot die coating device; extruding the two mixed solutions simultaneously from the slot die coating device onto a conveyor belt, then transporting the conveyor belt coated with the two mixed solutions to an oven for heating to form a self-supporting film; and carrying out thermal curing or infrared curing for the self-supporting film to convert remaining amide groups to imide groups completely to form a multi-layer polyimide film. | 01-07-2010 |
Syh-Yuh Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090162697 | CHLORINE, FLUORINE AND LITHIUM CO-DOPED TRANSPARENT CONDUCTIVE FILMS AND METHODS FOR FABRICATING THE SAME - A chlorine, fluorine and lithium co-doped transparent conductive film is provided, including chlorine, fluorine and lithium co-doped tin oxides, wherein the chlorine, fluorine and lithium co-doped tin oxides have a chlorine ion doping concentration not greater than 5 atom %, a fluorine ion doping concentration not greater than 5 atom %, and a lithium ion doping concentration not greater than 5 atom %. | 06-25-2009 |
Tin-Wen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080217621 | ACTIVE DEVICE ARRAY SUBSTRATE - A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate to cover the scan lines, the data lines and the active devices. Then, a plasma treatment is performed to the surface of the organic material layer to form a number of concave patterns. The dimension of each of the concave patterns is smaller than one micrometer. Afterward, pixel electrodes are formed on the organic material layer and each of the pixel electrodes is electrically connected to one of the corresponding active devices. | 09-11-2008 |
Tzyy-Ming Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080220574 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 09-11-2008 |
| 20080237734 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor. | 10-02-2008 |
| 20080242031 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 10-02-2008 |
| 20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 07-02-2009 |
| 20090239347 | METHOD OF FORMING MOS DEVICE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 09-24-2009 |
| 20110097868 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 04-28-2011 |
| 20110104864 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 05-05-2011 |
| 20110156156 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. | 06-30-2011 |
| 20110254064 | SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE - An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer. | 10-20-2011 |
| 20120009745 | METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR - A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure. | 01-12-2012 |
William Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110049516 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 03-03-2011 |
Wood-Hi Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090014847 | INTEGRATED CIRCUIT PACKAGE STRUCTURE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURE - An integrated circuit (IC) package structure with an electromagnetic interference (EMI) shielding structure utilizes double-layer successive cladding process. A dielectric coating layer and an EMI shielding layer material are sequentially coated on surface of a carrying substrate, an IC on the carrying substrate, and all the other devices. The EMI shielding layer is closely adhered to and bonded on a ground metal area exposed on an upper surface of the carrying substrate, the EMI shielding layer on the package is connected to a ground plane under the carrying substrate in series, so as to form a protection cover having a closed EMI shielding space to isolate the interference of electromagnetic waves from outside. | 01-15-2009 |
Yen-Chien Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110310718 | METHOD AND APPARATUS FOR JUDGING BLANK AREA AND DATA RECORDED-AREA OF OPTICAL DISC - An apparatus for judging an optical disc includes a gain controller, an amplitude detecting unit and an amplitude comparing unit. The gain controller is used for receiving a radio frequency signal from an optical pickup head; and processing the radio frequency signal into an amplified radio frequency signal with a target amplitude according to an amplitude feedback signal. The amplitude detecting unit is used for receiving the amplified radio frequency signal, generating the amplitude feedback signal to the gain controller, and outputting a top envelope amplitude according to an top envelope signal of the amplified radio frequency signal. The amplitude comparing unit is used for comparing the top envelope amplitude with a threshold value to generate a resulting signal, and judging whether the laser beams emitted from the optical pickup head are irradiated on a blank area or a data-recorded area according to the resulting signal. | 12-22-2011 |
Yu-Jen Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110112678 | ADVANCED PROCESS CONTROL FOR NEW TAPEOUT PRODUCT - The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe. | 05-12-2011 |
Yu-Ming Cheng, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120063756 | PHOTOGRAPHIC DEVICE HAVING OPTICAL IMAGE STABILIZATION MODULE AND OPTICAL IMAGE STABILIZATION PHOTOGRAPHIC DEVICE HAVING PERIPHERAL DRIVER CHIP - A photographic device having an optical image stabilization (OIS) module includes a compensation unit, a first position sensor, a second position sensor, a first vibration detection unit, a second vibration detection unit, a first actuator, a second actuator and a central processing unit (CPU). The CPU includes an anti-shake processing unit. The anti-shake processing unit processes vibration signals output by the first vibration detection unit and the second vibration detection unit and position signals output by the first position sensor and the second position sensor, and drives the first actuator and the second actuator to adjust positions of the compensation unit in the first direction and in the second direction and further compensate the shake of the photographic device having the OIS module in the first direction and in the second direction. | 03-15-2012 |