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Cheng-Chi
Cheng-Chi Chang, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100331249 | Pharmaceutical composition for inhibiting peritoneal dissemination - A pharmaceutical composition for treating or preventing peritoneal dissemination is provided. The pharmaceutical composition includes an effective dose of connective tissue growth factor (CTGF) and an acceptable receptor thereof. | 12-30-2010 |
Cheng-Chi Lin, Toechen Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20120086052 | HIGH VOLTAGE MOS DEVICE AND METHOD FOR MAKING THE SAME - A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided. | 04-12-2012 |
Cheng-Chi Lin, Toucheng Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090256183 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
| 20090256184 | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor - A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices. | 10-15-2009 |
| 20110121373 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern. The patterned second gate structure may include at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure. | 05-26-2011 |
| 20110140201 | LATERAL POWER MOSFET STRUCTURE AND METHOD OF MANUFACTURE - A lateral power MOSFET with a low specific on-resistance is described. Stacked P-top and N-grade regions in patterns of articulated circular arcs separate the source and drain of the transistor. | 06-16-2011 |
| 20110169137 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes. | 07-14-2011 |
| 20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
| 20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 02-02-2012 |
Cheng-Chi Lin, Yilan TW
| Patent application number | Description | Published |
|---|---|---|
| 20090209075 | LATERALLY DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR FABRICATING THE SAME - The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region. | 08-20-2009 |
Cheng-Chi Lin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080315308 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE AND METHOD OF FABRICATING THE SAME - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 12-25-2008 |
| 20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 08-25-2011 |
Cheng-Chi Tai, Tainan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090026861 | GENERATOR FOR EXERCISE EQUIPMENT - A generator for exercise equipment includes a disc and a case. The case has a surface. A number of first locating holes are disposed on the surface to accommodate coils therein. The case is pivotally connected to the disc. The case has an inner wall. A number of second locating holes are disposed on the inner wall of the case to accommodate magnets therein. By spinning, the disc is spinning with respect to the case so that the electricity is generated thereafter. | 01-29-2009 |
Cheng-Chi Tai, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100298677 | WIRELESS RING-TYPE PHYSICAL DETECTOR - A wireless ring-type physical detector includes a ring, a sensor unit, an amplifier unit, a demultiplexer unit, a processor unit and a wireless transmission unit. The sensor unit uses a light signal to detect the blood oxygen saturation, the heartbeat and continuous blood pressure. The detected light signal is processed by each unit to get a physical parameter which is valuable for a clinic test. | 11-25-2010 |
Cheng-Chi Wang, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090317837 | CANCER DIAGNOSIS BASED ON LEVELS OF ANTIBODIES AGAINST GLOBO H AND ITS FRAGMENTS - A cancer diagnostic method using a glycan array that contains Gb5 and Globo H, Bb2, Bb3, and/or Bb4. | 12-24-2009 |
| 20100247571 | METHODS AND COMPOSITIONS FOR IMMUNIZATION AGAINST VIRUS - Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41. | 09-30-2010 |
Cheng-Chi Wang, Ping Chen City TW
Cheng-Chi Wu, Nantou TW
| Patent application number | Description | Published |
|---|---|---|
| 20100019774 | ISOLATION CELL WITH TEST MODE - An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode. | 01-28-2010 |
Cheng-Chi Wu, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100179625 | Implantable Heating Apparatus for a Living Being and Method for Charging the Same - An implantable heating apparatus for a living being of the present invention includes a heating unit, a control unit for controlling operations of the heating unit and an induction driven charge/discharge unit for powering the heating unit. The induction driven charge/discharge unit is composed of a core, a coil set wrapping around the core in at least three axial directions and an energy storing unit for electrically coupling to the coil set. Such that when an external alternate magnetic field is approaching the induction driven charge/discharge unit, the coil set is able to generate induction current that can be stored in the energy storing unit. | 07-15-2010 |
| 20110068273 | Device and Method for Detecting High Energy Radiation Through Photon Counting - The present invention relates to a radiation-detecting device and an associated detection method. The detection device includes a scintillation crystal and an avalanche photodiode. The surface of the scintillation crystal is coated with a high-reflection layer. When ionizing radiation irradiates the scintillation crystal, the crystal emits luminescence, which passes through or is reflected by the high-reflection layer at least once within the scintillation crystal before it is received by the avalanche photodiode, generating a detection signal. | 03-24-2011 |
Cheng-Chi Wu, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110311772 | RESIN SURFACE LAYER AND METHOD OF FABRICATING THE SAME, COMPOSITE HAVING THE RESIN SURFACE LAYER AND METHOD OF FABRICATING THE SAME - A resin surface layer and a method of fabricating the same, and a composite having the resin surface layer and a method of fabricating the same are provided. The method of fabricating the resin surface layer includes: (a) providing a base, made of a resin and including a plurality of additive particles randomly distributed in the base; (b) changing the orientation of the additive particles to arrange the additive particles in a predetermined form; and (c) drying the base to make a surface of the base exhibit a visual effect of 3D texture. Thus, the visual effect of any 3D texture can be achieved by controlling the orientation of the additive particles. | 12-22-2011 |
Cheng-Chi Yen, Tainan TW
| Patent application number | Description | Published |
|---|---|---|
| 20100001934 | Display Panel and Multi-Branch Pixel Structure Thereof - A multi-branch pixel structure of display panel, such as LCoS, is disclosed. Each pixel cell of the display panel has at least two branches. The display panel has a pair of sub-data lines for each column of the pixel cells, and the sub-data lines are controllably coupled to the two branches respectively. The two branches enter an addressing mode and a displaying mode in turn, thereby substantially increasing operating speed and reducing coupling effect. | 01-07-2010 |
| 20100001937 | System and Method for Driving a Display Panel - A multi-branch pixel structure of a display panel, such as a liquid crystal on silicon (LCoS) panel, is disclosed. Each pixel cell of the display panel has at least two branches. For each column, two sub-data lines are coupled from a data driver. A multiplexer is configured to multiplex the sub-data lines between the adjacent pixel cells, such that multiplexed output of the multiplexer is coupled to a shared data line that is shared between the adjacent pixel cells, thereby substantially decreasing the pixel pitch. | 01-07-2010 |