Patent application number | Description | Published |
20140167187 | N Metal for FinFET - An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer. | 06-19-2014 |
20150183080 | APPARATUS AND METHOD FOR CHEMICAL MECHANICAL POLISHING - An apparatus for chemical mechanical polishing includes a wafer carrier, a first electrode, a rotatable pedestal, a second electrode, and an electric current detector. The first electrode is disposed at the wafer carrier. The rotatable pedestal is positioned opposite to the wafer carrier in order to perform a polishing operation with the wafer carrier accordingly. The second electrode is disposed at the rotatable pedestal and electrically coupled to the first electrode in order to form a circuit loop. The electric current detector is between the first electrode and the second electrode. | 07-02-2015 |
20150200100 | N Metal for FinFET and Methods of Forming - An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer. | 07-16-2015 |
20150371847 | METHOD FOR CONTROLLING SEMICONDUCTOR DEPOSITION OPERATION - The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof. | 12-24-2015 |
Patent application number | Description | Published |
20090088996 | Jitter measuring system and method - The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter. | 04-02-2009 |
20120146693 | APPARATUS FOR CLOCK SKEW COMPENSATION - An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module. | 06-14-2012 |
20130241661 | VOLTAGE-CONTROLLED OSCILLATOR MODULE AND METHOD FOR GENERATING OSCILLATOR SIGNALS - A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided. | 09-19-2013 |
20130278341 | RADIO FREQUENCY FRONT-END CIRCUIT AND OPERATION METHOD THEREOF - A radio frequency (RF) front-end circuit and an operating method thereof are provided. The proposed RF front-end circuit includes a first linear amplifier, a second linear amplifier, and a calibration unit. The first linear amplifier performs a high-frequency amplification on a RF signal to generate an amplified RF signal, and down-converts the amplified RF signal into an intermediate frequency (IF) signal. The second first linear amplifier performs a low-frequency amplification on the IF signal to generate an amplified IF signal. The calibration unit is coupled to the first and the second linear amplifiers, and receives a voltage gain fed back from the second linear amplifier. Then, the calibration unit performs an auto-calibration procedure according to the voltage gain fed back from the second linear amplifier to search for an input current value of the first linear amplifier, which correspondingly maximizes the voltage gain of the first amplifier. | 10-24-2013 |
20140139273 | CURRENT REUSE FREQUENCY DIVIDER AND METHOD THEREOF AND VOLTAGE CONTROL OSCILLATOR MODULE AND PHASE-LOCKED LOOP USING THE SAME - A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal. | 05-22-2014 |
Patent application number | Description | Published |
20120295437 | METHOD FOR FABRICATING THROUGH-SILICON VIA STRUCTURE - A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via. | 11-22-2012 |
20120305403 | Electrical Chemical Plating Process - An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure. | 12-06-2012 |
20130045595 | METHOD FOR PROCESSING METAL LAYER - The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz. | 02-21-2013 |
20130049141 | METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer. | 02-28-2013 |
20130178063 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SILICON THROUGH VIA - A method of manufacturing semiconductor device having silicon through via is disclosed, and conductor can be fully filled in the silicon through via. First, a silicon substrate is provided. Then, the silicon substrate is etched to form a through silicon via (TSV), and the through silicon via extends down from a surface of the silicon substrate. Next, a barrier layer is formed on the silicon substrate and in the through silicon via. Then, a seed layer is formed on the barrier layer and in the through silicon via. Afterward, a wet treatment is performed on the seed layer over the silicon substrate and within the through silicon via. The through silicon via is then filled with a conductor. | 07-11-2013 |
20130320537 | THROUGH SILICON VIA (TSV) STRUCTURE AND PROCESS THEREOF - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 12-05-2013 |
20130334690 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided. | 12-19-2013 |
20140057434 | THROUGH SILICON VIA PROCESS - A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer. | 02-27-2014 |
20140120711 | METHOD OF FORMING METAL GATE - Provided is a method of forming a metal gate including the following steps. A dielectric layer is formed on a substrate, wherein a gate trench is formed in the dielectric layer and a gate dielectric layer is formed in the gate trench. A first metal layer is formed in the gate trench by applying a AC bias between a target and the substrate during physical vapor deposition. A second metal layer is formed in the gate trench by applying a DC bias between the target and the substrate during physical vapor deposition. | 05-01-2014 |
20140239419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially. | 08-28-2014 |
20140306273 | STRUCTURE OF METAL GATE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer. | 10-16-2014 |
20140346616 | TRANSISTOR AND SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided. | 11-27-2014 |
20150061042 | METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer. | 03-05-2015 |
20150093893 | PROCESS OF FORMING SEED LAYER IN VERTICAL TRENCH/VIA - In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process. | 04-02-2015 |
20150340280 | THROUGH SILICON VIA (TSV) PROCESS - A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided. | 11-26-2015 |
Patent application number | Description | Published |
20130325229 | POWER CONTROL DEVICE FOR ELECTRIC VEHICLE - A power control device is adapted for controlling output power of an electric vehicle including a motor, an accelerator pedal, and a sensing module that senses an accelerator pedal depth and a vehicle speed to provide a sensed pedal depth and a sensed vehicle speed. The power control device includes a condition judging module operable to make a judgment of at least one of an acceleration condition, a starting condition, and a load condition based on the sensed pedal depth and the sensed vehicle speed from the sensing module, and a control module operable to generate a torque output signal according to the judgment made by the condition judging module, so as to control an output torque of the motor. | 12-05-2013 |
20140076979 | THERMOSTATIC ASSEMBLY FOR POWER MEMBERS OF AN ELECTRIC VEHICLE AND THE OPERATING PROCESS THEREOF - A thermostatic assembly for power members of an electric vehicle includes a pipe set having a main pipe and a recycle pipe, one end of the main pipe connected to one side of the pump, a plurality of temperature-adjusting pipes connected between another end of the main pipe and one end of the recycle pipe, another end of the recycle pipe connected to another side of the pump, a plurality of power members respectively set on the temperature-adjusting pipes, a input change valve set between the main pipe and each temperature-adjusting pipe, a output change valve set between the recycle pipe and each temperature-adjusting pipe, a controller electrically connected to the input change valve, the output change valve and each power member. Under this arrangement, the controller ranks a sequence of the temperature information and defines a sequence of the flow direction of the temperature-adjusting water. | 03-20-2014 |
20150175012 | Energy Management Device and Method for a Vehicle - An energy management device includes an energy transfer unit, and a control unit that generates a control signal based at least on a residual electric quantity of each of high power and high energy storage devices of a vehicle, whether the energy transfer unit is coupled to an external energy source, and a position of the vehicle. The energy transfer unit performs, based on the control signal, energy transfer among the external energy source, the high power and high energy storage devices, and at least one energy load of the vehicle. | 06-25-2015 |
Patent application number | Description | Published |
20130252668 | CELLULAR WITH AN EXTENSION DISPLAY - A portable communication device includes a control unit, a main display and an extension display coupled to the control unit. The display area of the extension is larger than the one of the main display for displaying at least a part of the web page information or image (video) information. A driver is in responsive to the extension display interface to driver the extension display out of the cellular, wherein a finger of a user slide the extension slide bar on the main touch display, the driver being responsive the sliding to drive the extension display in or out of the cellular. | 09-26-2013 |
20140267551 | Device with Background Composition Module - A portable communication, comprises a control unit, a display coupled to the control unit; a memory is coupled to the control unit. A background database is stored in the memory, wherein a background is selected from the background database; a background composition module is coupled with the control unit for composting user input signal and the selected background to generated a composted signal; and followed by transmitting the composited signal. | 09-18-2014 |
20150138129 | PORTABLE DEVICE WITH AN ARRAY OF CAPACITORS ON A REAR SURFACE OF A DISPLAY - A portable communicating device with an array of capacitors includes a control unit; a communication module is coupled to the control unit; a memory is coupled to the control unit; an antenna is coupled to the communication module; a display is coupled to the control unit and wherein the display includes a front side and a rear side, an image is displayed on the front side; an array of capacitors formed on the rear side to provide electricity. The capacitors include a first node and a second node. The first node and the second node include carbon nanotube, grapheme, conductive polymer or the combination to achieve the purpose of flexible purpose, thereby providing the bending display with flexible power supply. | 05-21-2015 |