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| 20080261071 | Preserving Solderability and Inhibiting Whisker Growth in Tin Surfaces of Electronic Components - A method for reducing whisker formation and preserving solderability in tin coatings over metal features of electronic components. The tin coating has internal tensile stress and is between about 0.5 m and about 4.0 m in thickness. There is a nickel-based layer under the tin coating. | 10-23-2008 |
| 20080278029 | ELECTROLESS PLATING PRODUCTION OF NICKEL AND COLBALT STRUCTURES - A method comprising forming a structural element | 11-13-2008 |
| 20090145764 | COMPOSITE COATINGS FOR WHISKER REDUCTION - There is provided a method and composition for applying a wear resistant composite coating onto a metal surface of an electrical component. The method comprises contacting the metal surface with an electrolytic plating composition comprising (a) a source of tin ions and (b) non-metallic particles, and applying an external source of electrons to the electrolytic plating composition to thereby electrolytically deposit the composite coating onto the metal surface, wherein the composite coating comprises tin metal and the non-metallic particles. | 06-11-2009 |
| 20090145765 | COMPOSITE COATINGS FOR WHISKER REDUCTION - There is provided a method and composition for applying a wear resistant composite coating onto a metal surface of an electrical component. The method comprises contacting the metal surface with an electrolytic plating composition comprising (a) a source of tin ions and (b) non-metallic particles, and applying an external source of electrons to the electrolytic plating composition to thereby electrolytically deposit the composite coating onto the metal surface, wherein the composite coating comprises tin metal and the non-metallic particles. | 06-11-2009 |
| 20100294669 | ELECTROLYTIC DEPOSITION OF METAL-BASED COMPOSITE COATINGS COMPRISING NANO-PARTICLES - A method is provided for imparting corrosion resistance onto a surface of a substrate. The method comprises contacting the surface of the substrate with an electrolytic plating solution comprising (a) a source of deposition metal ions of a deposition metal selected from the group consisting of zinc, palladium, silver, nickel, copper, gold, platinum, rhodium, ruthenium, chrome, and alloys thereof, (b) a pre-mixed dispersion of non-metallic nano-particles, wherein the non-metallic particles have a pre-mix coating of surfactant molecules thereon; and applying an external source of electrons to the electrolytic plating solution to thereby electrolytically deposit a metal-based composite coating comprising the deposition metal and non-metallic nano-particles onto the surface. | 11-25-2010 |
| 20110215068 | ELECTROLESS PLATING PRODUCTION OF NICKEL AND COBALT STRUCTURES - A method comprising forming a structural element | 09-08-2011 |
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| 20080237447 | ULTRA LOW VOLTAGE CMOS IMAGE SENSOR ARCHITECTURE - An optical sensor has at least one pixel that generates an output voltage that changes at a rate dependent on the light intensity incident on the pixel. The time for the pixel output voltage to change from a first predefined level to a second predefined level is measured, so as to produce an output indicative of the incident light intensity. | 10-02-2008 |
| 20100128154 | SYSTEMS AND METHODS TO PROVIDE REFERENCE CURRENT WITH NEGATIVE TEMPERATURE COEFFICIENT - Systems and methods for providing one or more reference currents with respective negative temperature coefficients are provided. A first voltage is divided to provide a divided voltage, which is compared to a reference voltage (e.g., a bandgap reference voltage) to provide a control voltage. The first voltage and the one or more reference currents are based on the control voltage. | 05-27-2010 |
| 20100243866 | IMAGING DEVICES AND METHODS FOR CHARGE TRANSFER - A pixel circuit having improved charge transfer including an amplifier having an input node electrically connected to a charge storage node of the pixel circuit, and a negative feedback control loop having a capacitance element electrically connected between the input node and an output node of said amplifier. | 09-30-2010 |
| 20120013780 | OPTICAL BLACK PIXEL CELL READOUT SYSTEMS AND METHODS - This is generally directed to systems and methods for reading optical black pixel cells. For example, in some embodiments, the columns of a pixel array can be shunted together during an optical black pixel readout phase of the imaging system. This may, for example, help improve correction of column fixed pattern noise or other noise. In some embodiments, the column may be shunted together during the optical black pixel readout phase of the imaging system and not shunted during other phases of the imaging system (e.g., when reading values from active pixel cells, barrier pixel cells, etc). In some embodiments, circuitry for providing the column shunting can be implemented as an independent block of the imaging system. In other embodiments, this circuitry can be implemented within other blocks of the imaging system. As an illustration, the shunting circuitry can be implemented within a VLN block of the imaging system. | 01-19-2012 |
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| 20090160979 | Methods and apparatuses for double sided dark reference pixel row-wise dark level non-uniformity compensation in image signals - Methods and apparatuses for row-wise dark level non-uniformity compensation of imaging sensor pixel signals. A column dependent dark reference value is determined as one of a linear and parabolic function of signal values from two areas of dark reference pixels and a column location and then used for dark level non-uniformity compensation of signal values from imaging pixels. | 06-25-2009 |
| 20090190005 | Method and apparatus providing pixel-wise noise correction - Methods and apparatuses providing pixel-wise noise correction using pixels to provide reference values during pixel readout operations. | 07-30-2009 |
| 20100163933 | ANTIBLOOMING IMAGING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time. | 07-01-2010 |
| 20100219342 | ANTIBLOOMING IMAGING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time. | 09-02-2010 |
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| 20080198251 | Method, apparatus, and system providing multiple pixel integration periods - A method, apparatus and system providing high dynamic range operation for an image sensor by using signals from multiple pixels having different integration times. | 08-21-2008 |
| 20090040349 | Imager methods, apparatuses, and systems providing a skip mode with a wide dynamic range operation - Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an array are not readout. Multiple integration periods are employed in the skip mode with selected pixels being readout through circuits associated with pixels that are not readout. | 02-12-2009 |
| 20090045320 | Method, apparatus and system for a low power imager device - A method, apparatus and system providing an imaging device in which a bias current supplied to one or more imaging device circuits is adjusted in accordance with a frequency of a pixel clock signal. | 02-19-2009 |
| 20090073289 | Method and apparatus for providing a rolling double reset timing for global storage in image sensors - An apparatus for and a method of operating an array of pixels of an image sensor, where each pixel includes at least a photosensor, an associated storage device and a floating diffusion region and the array of pixels is configured in a plurality of rows and columns. The photosensors associated with the pixels are reset and charges are accumulated in the photosensor. The accumulated charges are then globally transferred to storage devices associated with the pixels. A rolling double reset is used to reduce the deleterious effects on the accumulated charges stored in the storage devices. The accumulated charges stored in the storage devices are transferred to floating diffusion regions associated with the pixels and the charges residing in the floating diffusion region are read out. In a second embodiment the storage device is eliminated and the rolling double reset is used to reduce the deleterious effects on the accumulated charges stored in the floating diffusion region. | 03-19-2009 |
| 20090273691 | METHOD AND APPARATUS PROVIDING ANALOG ROW NOISE CORRECTION AND HOT PIXEL FILTERING - An imaging device and method for operating the device. The imaging device comprises a pixel array that comprises a plurality of imaging pixels and dark reference pixels arranged in columns and rows. The dark reference pixels produce a noise signal that is subtracted from a pixel signal produced by the imaging pixels to correct row noise. In addition, the imaging device may comprise a hot pixel filtering circuit that blocks the output from hot pixels. | 11-05-2009 |
| 20090316466 | METHOD, APPARATUS AND SYSTEM, PROVIDING A ONE-TIME PROGRAMMABLE MEMORY DEVICE - Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed. | 12-24-2009 |
| 20110199522 | IMAGER METHODS, APPARATUSES, AND SYSTEMS PROVIDING A SKIP MODE WITH A WIDE DYNAMIC RANGE OPERATION - Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an array are not readout. Multiple integration periods are employed in the skip mode with selected pixels being readout through circuits associated with pixels that are not readout. | 08-18-2011 |
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| 20080240618 | Image-document retrieving apparatus, method of retrieving image document, program, and recording medium - Feature vectors used in discrimination of images include information on feature blocks of images in an image-document retrieving apparatus of the present invention. Text areas of a page image document are combined to form rectangular images. On the basis of information on the rectangular images that are extracted, a geometric structure of the page is analyzed, the page image document is divided into plural blocks, and then a plurality of feature blocks describing features of the page document image are selected from the plural blocks. The feature vectors are constituted of information on the feature blocks thus selected. This makes it possible to provide an image-document retrieving apparatus and a method of retrieving image documents, by which retrieval of image documents containing mainly text and a graphic is improvable in accuracy. | 10-02-2008 |
| 20080244378 | Information processing device, information processing system, information processing method, program, and storage medium - An information processing device includes: a feature extracting section for extracting, as format information, a format feature of a process-target document from image data of the process-target document, on which filling-in spaces of plural items are printed; a document recognizing section for comparing the format information of the process-target document with registered format information stored in a storage device, and specifying a registered document that corresponds to the process-target document, the registered format information regarding format features of registered documents; a data acquiring section for converting characters in the image data of the process-target document into text data; and a distributing section for grouping the image data and text data of the characters into plural groups according to a separation rule that is set for the registered document, the characters being written in the fill-in spaces of the items of the process-target document, and for transmitting the different groups to different external devices. With this, information such as personal information to be protected can be processed, preventing an operator dealing with the information from obtaining the whole information. | 10-02-2008 |
| 20110246959 | METHOD, SYSTEM, AND DESIGN STRUCTURE FOR MAKING VOLTAGE ENVIRONMENT CONSISTENT FOR REUSED SUB MODULES IN CHIP DESIGN - The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period. | 10-06-2011 |
| 20120047478 | Method For Estimating The Latency Time Of A Clock Tree In An Asic Design - Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design. | 02-23-2012 |
