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Chen, Sunnyvale
Bee-Chung Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080306945 | EXAMPLE-DRIVEN DESIGN OF EFFICIENT RECORD MATCHING QUERIES - Example-driven creation of record matching queries. The disclosed architecture employs techniques that exploit the availability of positive (or matching) and negative (non-matching) examples to search through this space and suggest an initial record matching query. The record matching task is modeled as that of designing an operator tree obtained by composing a few primitive operators. This ensures that record matching programs be executable efficiently and scalably over large input relations. The architecture joins records across multiple (e.g., two) relations (e.g., R and S). The architecture exploits the monotonicity property of similarity functions for record matching in the relations, in that, any pair of matching records have a higher similarity value than non-matching record pairs on at least one similarity function. | 12-11-2008 |
| 20090063984 | Customized today module - A method and apparatus for customizing content presented to individual users or user segments is provided. There may be three components, a web portal and toolbar component, a modeling component, and a scoring component. The web portal and toolbar component presents content items and collects data. The web portal and toolbar component generates user event data based on the user actions. The user event data is forwarded to the modeling component. The modeling component generates content scoring functions based on user event data and attributes of content items. Content scoring functions may be unique to individual user segments. The content scoring functions based on content features generate probability a content item will be viewed. The scoring component decides which content items are placed in a portal. The scoring component uses the scoring functions generated by the modeling component to rank content items in real time. | 03-05-2009 |
Changyuan Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090016113 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 01-15-2009 |
| 20090096507 | Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor - An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results. | 04-16-2009 |
| 20090290430 | Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array - A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line. | 11-26-2009 |
| 20100220533 | NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE - Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate. | 09-02-2010 |
| 20100322015 | Split Gate NAND Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing - A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto. | 12-23-2010 |
| 20110170358 | PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target. | 07-14-2011 |
Charles L. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100073329 | Quick Gesture Input - A computer-implemented user interface method for a computing device is disclosed. The method includes associating each of a plurality of telephone keys with a direction of each key relative to a center of a telephone keypad, receiving a contact from a user of the device at a location on a touchscreen display of a computing device and an input at a direction relative to the location of the user contact, and causing a telephone number to be entered on the computing device based on the direction of each key relative to the center of the telephone keypad corresponding to the direction relative to the location of the user contact. | 03-25-2010 |
| 20110238735 | Trusted Maps: Updating Map Locations Using Trust-Based Social Graphs - A system and method for updating and correcting the location of geospatial entities, the method comprising receiving at a server from a mobile device operated by a first user, a proposed location for a geospatial entity, the proposed location determined by a wireless location system, and based upon a current location of the mobile device; providing information about the proposed location for the geospatial entity to a first plurality of other users; receiving votes from the first plurality of users as to whether the proposed location is correct and responsive to the received votes, determining whether to update the location information for the geospatial entity. | 09-29-2011 |
Chih Liang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090300237 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 12-03-2009 |
| 20110182128 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 07-28-2011 |
Chiliang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080286984 | SILICON-RICH LOW-HYDROGEN CONTENT SILICON NITRIDE FILM - In one embodiment, a method for forming a silicon nitride film is provided. The method includes providing a plasma-enhanced chemical vapor deposition (PECVD) reactor with a semiconductor substrate therein; flowing a gas mixture consisting of silane and nitrogen into the PECVD reactor; and forming a plasma in the PECVD reactor, whereby the silicon nitride film is deposited on the semiconductor substrate. | 11-20-2008 |
| 20090039413 | METHOD TO FORM UNIFORM TUNNEL OXIDE FOR FLASH DEVICES AND THE RESULTING STRUCTURES - Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated. | 02-12-2009 |
| 20090096009 | NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE - A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer ( | 04-16-2009 |
Chunnuan Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110055192 | FULL TEXT QUERY AND SEARCH SYSTEMS AND METHOD OF USE - Roughly described, a database searching method for searching a database, in which hits are ranked in dependence upon an information measure of itoms shared by both the hit and the query. The information measure can be a Shannon information score, or another measure which indicates the information value of the shared itoms. An itom can be a word or other token, or a multi-word phrase, and can overlap with each other. Synonyms can be substituted for itoms in the query, with the information measure of substituted itoms being derated in accordance with a predetermined measure of the synonyms' similarity. Indirect searching methods are described in which hit from other search engines are re-ranked in dependence upon the information measures of shared itoms. Structured and completely unstructured databases may be searched, with hits being demarcated dynamically. Hits may be clustered based upon distances in an information-measure-weighted distance space. | 03-03-2011 |
Crystal Rhan-Tsor Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090079744 | ANIMATING OBJECTS USING A DECLARATIVE ANIMATION SCHEME - Technologies are described herein for animating objects through the use of animation schemes. An animation scheme is defined using a declarative language that includes instructions defining the animations and/or visual effects to be applied to one or more objects and how the animations or visual effects should be applied. The animation scheme may include rules which, when evaluated, define how the objects are to be animated. An animation scheme engine is also provided for evaluating an animation scheme along with other factors to apply the appropriate animation to each of the objects. The animation scheme engine retrieves an animation scheme and data regarding the objects. The animation scheme engine then evaluates the animation scheme along with the data regarding the objects to identify the animation to be applied to each object. The identified animations and visual effects are then applied to the objects. | 03-26-2009 |
Daniel Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100318763 | SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE - Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses. | 12-16-2010 |
Dongni Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100161590 | QUERY PROCESSING IN A DYNAMIC CACHE - The subject matter disclosed herein relates to dynamically update an ad cache. | 06-24-2010 |
Edmund Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100278190 | HIERARCHICAL PIPELINED DISTRIBUTED SCHEDULING TRAFFIC MANAGER - A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic. | 11-04-2010 |
Edmund G. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080259928 | Method and Apparatus for Out-of-Order Processing of Packets using Linked Lists - These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets. | 10-23-2008 |
| 20080259960 | Method and apparatus for Out-of-Order Processing of Packets - A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets. | 10-23-2008 |
| 20110286463 | HIGH PERFORMANCE HARDWARE LINKED LIST PROCESSORS - In one embodiment, a reassign command is received for reassigning a first node identified by a first global identifier (GID) from a first context identified by a first context ID (CID) to a second context identified by a second CID, the first and second contexts representing first and second linked lists, respectively. A walk-the-chain (WTC) command having the first GID and the first CID is issued to a first linked list processor. The first linked list processor is configured to access one or more nodes of the first context in an attempt to dequeue the first node from the first context. An enqueue command having the first GID and the second CID is issued to a second linked list processor. The second linked list processor is configured to insert the first node to the second context. The first and second linked list processors are cascaded to form a pipeline. | 11-24-2011 |
Fusen Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090233438 | SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING - A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets. | 09-17-2009 |
Haibin Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090055944 | HUMAN MONOCLONAL ANTIBODIES TO BE PROGRAMMED DEATH LIGAND 1 (PD-L1) - The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to PD-L1 with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The disclosure also provides methods for detecting PD-L1, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PD-L1 antibodies. | 02-26-2009 |
| 20100330078 | ALPHA 5 - BETA 1 ANTIBODIES AND THEIR USES - The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies, or antigen binding portions thereof, that specifically bind to integrin α5β1 with high affinity. Nucleic acid molecules encoding the antibodies of the disclosure, expression vectors, host cells and methods for expressing the antibodies of the disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies or antigen binding portions thereof are also provided. The disclosure also provides methods for treating various cancers using the anti-α5β1 antibodies or antigen binding portions thereof described herein. | 12-30-2010 |
| 20110209230 | Human Monoclonal Antibodies To Programmed Death Ligand 1 (PD-L1) - The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to PD-L1 with high affinity. Nucleic acid molecules encoding the antibodies of this disclosure, expression vectors, host cells and methods for expressing the antibodies of this disclosure are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the antibodies of the invention are also provided. The disclosure also provides methods for detecting PD-L1, as well as methods for treating various diseases, including cancer and infectious diseases, using anti-PD-L1 antibodies. | 08-25-2011 |
Haichun Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110296364 | METHOD AND APPARATUS FOR CUSTOM MODULE GENERATION - Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout. | 12-01-2011 |
Howard H. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110167416 | SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS - Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution. | 07-07-2011 |
Hung Cih Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100099339 | POLISHING PAD EDGE EXTENSION - A method and apparatus for providing a substantially uniform pressure to a polishing surface from a conditioning element is provided. The method includes urging a conditioning disk against a polishing surface of a rotating polishing pad, moving the conditioning disk across the polishing surface in a sweep pattern that includes at least a portion of the conditioning disk extending over a peripheral edge of the polishing surface, and maintaining a substantially uniform pressure to the polishing surface from the conditioning disk across the sweep pattern. | 04-22-2010 |
Jesse Eugene Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100286807 | System and Method of Verification of Analog Circuits - In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers. | 11-11-2010 |
Jialing Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090183548 | METHOD AND APPARATUS FOR IN SITU TESTING OF GAS FLOW CONTROLLERS - Methods and apparatus utilize a rate of drop in pressure upstream of a gas flow controller (GFC) to accurately measure a rate of flow through the GFC. Measurement of the gas flow through the many gas flow controllers in production use today is enabled, without requiring any special or sophisticated pressure regulators or other special components. Various provisions ensure that none of the changes in pressure that occur during or after the measurement perturb the constant flow of gas through the GFC under test. | 07-23-2009 |
| 20090183549 | METHOD AND APPARATUS FOR IN SITU TESTING OF GAS FLOW CONTROLLERS - Methods and apparatus utilize a rate of drop in pressure upstream of a gas flow controller (GFC) to accurately measure a rate of flow through the GFC. Measurement of the gas flow through the many gas flow controllers in production use today is enabled, without requiring any special or sophisticated pressure regulators or other special components. Various provisions ensure that none of the changes in pressure that occur during or after the measurement perturb the constant flow of gas through the GFC under test. | 07-23-2009 |
| 20110011183 | METHOD AND APPARATUS FOR IN SITU TESTING OF GAS FLOW CONTROLLERS - Methods and apparatus utilize a rate of drop in pressure upstream of a gas flow controller (GFC) to accurately measure a rate of flow through the GFC. Measurement of the gas flow through the many gas flow controllers in production use today is enabled, without requiring any special or sophisticated pressure regulators or other special components. Various provisions ensure that none of the changes in pressure that occur during or after the measurement perturb the constant flow of gas through the GFC under test. | 01-20-2011 |
| 20110108126 | METHOD AND APPARATUS FOR GAS FLOW CONTROL - A method and apparatus for self-calibrating control of gas flow. The gas flow rate is initially set by controlling, to a high degree of precision, the amount of opening of a flow restriction, where the design of the apparatus containing the flow restriction lends itself to achieving high precision. The gas flow rate is then measured by a pressure rate-of-drop upstream of the flow restriction, and the amount of flow restriction opening is adjusted, if need be, to obtain exactly the desired flow. | 05-12-2011 |
Jianhua Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100245022 | Electrically activated surface mount thermal fuse - A reflowable thermal fuse includes a conduction element with first and second ends, disposed within a housing. The reflowable thermal fuse also includes an elastic element disposed within the housing and adapted to apply force on the conduction element in an activated state of the reflowable thermal fuse. A restraining element is utilized to secure the elastic element and prevent the elastic element from applying force on the conduction element in an installation state of the reflowable thermal fuse. Application of an activating current through the restraining element causes the restraining element to break and thereby release the elastic element and place the reflowable thermal fuse in the activated state. | 09-30-2010 |
| 20100245027 | Reflowable thermal fuse - A reflowable thermal fuse includes a positive-temperature-coefficient (PTC) device that defines a first end and a second end, a conduction element that defines a first end and a second end in electrical communication with the second end of the PTC device, and a restraining element that defines a first end in electrical communication with the first end of the PTC device and a second end, in electrical communication with a second end of the conduction element. The restraining element is adapted to prevent the conduction element from coming out of electrical communication with the PTC device in an installation state of the thermal fuse. During a fault condition, heat applied to the thermal fuse diverts current flowing between the first end of the PTC device and the second end of the conduction element to the restraining element, causing the restraining element to release the conduction element and activate the fuse. | 09-30-2010 |
| 20110050384 | Termal fuse - A thermal fuse includes a first contact surface connected to a top surface of a sensor and a bottom surface connected to a bottom surface of the sensor. The sensor includes a mixture of Sn and Zn. The distance between the top surface and the bottom surface of the sensor is sized to substantially limit Zn depletion in a center region of the sensor when a temperature of the sensor is below a melting temperature of the sensor. The center region of the sensor prevents the first contact surface and the second contact surface from separating when the temperature of the sensor is below the melting temperature, and the first contact surface and the second contact surface are configured to separate when the temperature of the center region of the sensor exceeds the melting temperature of the sensor. | 03-03-2011 |
Jian Ping Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100301375 | FORMULATION FOR IMPROVED ELECTRODES FOR ELECTRONIC DEVICES - A conductive electrode paste or ink formulation including a getter removes or reduces the concentration of the unwanted impurities in an electronic device. These reductions may happen during or immediately after the fabrication or sealing of the device, or they may occur after some activation time or event. Water, oxygen, carbon dioxide, hydrogen, and residual solvents are gettered. | 12-02-2010 |
| 20110057151 | IONIC SALT COMBINATIONS IN POLYMER ELECTROLUMINESCENT INKS - Luminescent ink formulations containing multiple salts selected for good ionic mobility, thermal stability, compatibility with light emitting polymers, good solubility in ink solvents, and electrochemical stability improve the performance of electroluminescent ink. As one salt may not contain all the required properties, a combination of salts is chosen based on the physical and chemical properties of different salts. When multiple salts are incorporated into a light emitting polymer layer, devices show improved lifetime and overall device performance. | 03-10-2011 |
Jia-Yi Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090296853 | Rotation Direction Control for Phase Modulation - A transmitter architecture and method of modulation that include a rotation-direction control circuit for varying the direction of rotation of phase transitions of a phase modulation based on the occurrence of a predetermined pattern of input data. This variation of rotation direction by the rotation-direction control circuit maintains the output spectrum of a modulated signal within the spectral mask requirements of an associated communications standard and thereby enables the use of non-linear power amplifiers in applications that generally require linear amplifiers. | 12-03-2009 |
Jingquan Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080278223 | APPARATUS AND METHOD FOR CONTROLLING THE PROPAGATION DELAY OF A CIRCUIT BY CONTROLLING THE VOLTAGE APPLIED TO THE CIRCUIT - The voltage applied to an integrated circuit is controlled by a temporal process monitor formed as part of the integrated circuit. The temporal process monitor includes a voltage controlled oscillator for producing a first output signal having a first period. A comparator compares the first period to one or more reference values. Should the first period be greater than a first selected reference value the comparator sends a signal to increase the voltage being supplied to the integrated circuit. Should the first period be less than a second selected reference value, the comparator sends a signal to decrease the voltage applied to the integrated circuit. In some embodiments a scaling circuit is provided for producing a second output signal having a second period different from (typically but not necessarily longer than) the first period. By placing the temporal process monitor on an integrated circuit chip, process variations and environmental factors which affect the performance of the integrated circuit can be automatically compensated so that the integrated circuit performs within specifications. Two or more temporal process monitors can be placed on a single integrated circuit chip or on different integrated circuit chips and the longest period produced by the temporal process monitors can be used to control the voltage supplied to all the sections of the integrated circuit chip associated with the temporal process monitors or to all the integrated circuit chips associated with the temporal process monitors. In some embodiments voltages related to the frequency of a temporal process monitor signal and the frequency of a fixed frequency clock are provided to an error amplifier, which changes the voltage applied to the integrated circuit such that the two frequencies are the same. | 11-13-2008 |
Keke Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080208836 | Regression framework for learning ranking functions using relative preferences - A method and apparatus for determining a ranking function by regression using relative preference data. A number of iterations are performed in which to following is performed. The current ranking function is used to compare pairs of elements. The comparisons are checked against actual preference data to determine for which pairs the ranking function mis-predicted (contradicting pairs). A regression function is fitted to a set of training data that is based on contradicting pairs and a target value for each element. The target value for each element may be based on the value that the ranking function predicted for the other element in the pair. The ranking function for the next iteration is determined based, at least in part, on the regression function. The final ranking function is established based on the regression functions. For example, the final ranking function may be based on a linear combination of regression functions. | 08-28-2008 |
| 20080301069 | SYSTEM AND METHOD FOR LEARNING BALANCED RELEVANCE FUNCTIONS FROM EXPERT AND USER JUDGMENTS - The present invention relates to systems and methods for determining a content item relevance function. The method comprises collecting user preference data at a search provider for storage in a user preference data store and collecting expert-judgment data at the search provider for storage in an expert sample data store. A modeling module trains a base model through the use of the expert-judgment data and tunes the base model through the use of the user preference data to learn a set of one or more tuned models. A measure (B measure) is designed to evaluate the balanced performance of tuned model over expert judgment and user preference. The modeling module generates or selects the content item relevance function from the tuned models with B measure as the selection criterion. | 12-04-2008 |
| 20090319507 | METHODS AND APPARATUSES FOR ADAPTING A RANKING FUNCTION OF A SEARCH ENGINE FOR USE WITH A SPECIFIC DOMAIN - Methods and apparatuses are provided for adapting hierarchical structure information associated with a first ranking function tuned for use in a first domain for use in a second domain. | 12-24-2009 |
Kok Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110249141 | METHOD AND APPARATUS FOR COLOR CORRECTION OF COLOR DEVICES FOR VARIOUS OPERATING CONDITIONS - Methods and apparatuses for color correction of color device for various operating conditions. In at least one embodiment of the present invention, operating under a current condition, a color correction operation that is derived from color correction operations defined for other conditions is performed on the color data. In another embodiment, a device profile for managing colors for a color device operating under one condition is interpolated from the device profiles for the color device operating under other conditions (e.g., based on the input received from a user interface according to the perception of the user or based on the measurement of a sensor). The interpolation can be based on the input received from a user interface according to the perception of the user or it can be based on the measurement of a sensor or a set of sensors. Various operating conditions for a color device (e.g., a scanner, a camera, a video camera, a printer, a display device such as a CRT monitor or an LCD display panel, a television set, or others) include chromaticity and illumination of ambient light, background color for a display device, characteristics of print media for a printer, humidity, temperature, pressure and ink level for an ink jet printer, the age of a light source for a scanner, and others. | 10-13-2011 |
Larry Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090037509 | WIDGET DISCOVERY IN COMPUTING DEVICES - A system and a method are disclosed for discovering widgets for computing devices. A computing device parses data to identify rich content. The computing device searches for widgets supporting the identified rich content in a remote server and retrieves a widget supporting the identified rich content. The computing device executes the widget to process the rich content. | 02-05-2009 |
Lei G. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100040078 | Method and Apparatus for Centralized Selection of a Control Network - An apparatus and method for centrally selecting a control network from redundant control networks is described. In one embodiment of the invention, a network element includes a first control network and a second control network. Each line card implements a bonding interface to bond a first port coupled with the first control network and a second port coupled with the second control network. On each line card, the first and second ports receive a control network selection message from the first and second control networks respectively. A link layer driver on each line card interprets those selection messages and determines which control network is active and reports that control network as up to the bonding interface and reports the other control network as down to the bonding interface. The bonding interface selects the control network reported as up and application software uses that control network. | 02-18-2010 |
Longbin Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100054535 | Video Object Classification - Techniques for classifying one or more objects in at least one video, wherein the at least one video comprises a plurality of frames are provided. One or more objects in the plurality of frames are tracked. A level of deformation is computed for each of the one or more tracked objects in accordance with at least one change in a plurality of histograms of oriented gradients for a corresponding tracked object. Each of the one or more tracked objects is classified in accordance with the computed level of deformation. | 03-04-2010 |
| 20100054540 | Calibration of Video Object Classification - Techniques for calibrating a classification system, wherein one or more objects in at least one video are classified, are provided. At least one view associated with the at least one video is obtained. The at least one view is partitioned into at least one region. A given object is classified in accordance with its location in reference to the at least one region. In an additional embodiment, one or more object models are obtained. At least one normalized size of the one or more objects is defined within at least one view associated with the at least one video in accordance with the one or more object models. The one or more objects are classified in accordance with the at least one defined normalized size. | 03-04-2010 |
| 20110022549 | Presenting Search Results Based on User-Customizable Criteria - In one embodiment, ranking search results generated in response to search queries comprises: receiving, a search query from a user; identifying a plurality of network contents in response to the search query; determining one or more ranking criteria for the search query; presenting the ranking criteria to the user; receiving from the user one or more weights assigned to one or more of the ranking criteria; ranking the identified network contents based on the ranking criteria and the weights; and presenting the network contents to the user in an order according to their ranking. | 01-27-2011 |
| 20110040769 | Query-URL N-Gram Features in Web Ranking - In one embodiment, access one or more pairs of search query and clicked Uniform Resource Locator (URL). For each of the pairs of search query and clicked URL, segment the search query into one or more query segments and the clicked URL into one or more URL segments; construct one or more query-URL n-grams, each of which comprises a query part comprising at least one of the query segments and a URL part comprising at least one of the URL segments; and calculate one or more association scores, each of which for one of the query-URL n-grams and represents a similarity between the query part and the URL part of the query-URL n-gram and is based on a first frequency of the query part and the URL part, a second frequency of the query part, and a third frequency of the URL part. | 02-17-2011 |
Lu Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100188657 | SYSTEMS AND METHODS FOR DETECTING DEFECTS ON A WAFER - Systems and methods for detecting defects on a wafer are provided. One method includes generating output for a wafer by scanning the wafer with an inspection system using first and second optical states of the inspection system. The first and second optical states are defined by different values for at least one optical parameter of the inspection system. The method also includes generating first image data for the wafer using the output generated using the first optical state and second image data for the wafer using the output generated using the second optical state. In addition, the method includes combining the first image data and the second image data corresponding to substantially the same locations on the wafer thereby creating additional image data for the wafer. The method further includes detecting defects on the wafer using the additional image data. | 07-29-2010 |
| 20110263111 | GROUP III-NITRIDE N-TYPE DOPING - Group III-nitride N-type doping techniques are described. | 10-27-2011 |
Ming-Fong Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110231420 | METHOD AND SYSTEM FOR AUTOMATICALLY INITIATING A FILE AGGREGATION PROCESS BETWEEN COMMUNICATIVELY COUPLED DEVICES - A method and system for automatically detecting a coupling of a storage device to one or more computing systems. The method automatically identifies a configuration specific to the computing system and accesses the configuration specific to the computing system. The method automatically identifies a plurality of files residing on the computing system corresponding to the configuration and automatically aggregates the plurality of files to the storage device. | 09-22-2011 |
Norman K. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080285435 | INTELLIGENT FAILBACK IN A LOAD-BALANCED NETWORKING ENVIRONMENT - One embodiment of the present invention sets forth a method for failing back network connections to a network interface card (NIC) within a computing device. The method includes the steps of monitoring a failed or unreliable NIC within the computing device, determining that the failed or unreliable NIC has recovered, determining that a functional NIC within the computing device is overloaded, selecting a first connection set communicating through the overloaded NIC, and transferring the first connection set to the recovered NIC. With this approach, intelligent decisions can be advantageously made regarding whether to fail back a network connection set to a recovered NIC based on the traffic loads on the overloaded NIC and the recovered NIC. Such an approach to balancing network traffic across the functional NICs within a computing device may substantially improve overall performance relative to prior art techniques. | 11-20-2008 |
| 20080285441 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
| 20080285448 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
| 20080285472 | INTELLIGENT FAILOVER IN A LOAD-BALANCED NETWORK ENVIRONMENT - A hash table in the network device driver maintains data on the traffic characteristics for each network interface (“NIC”) within a computing device. If one of the NICs in the computing device becomes unreliable, the cost function in the hash engine allows the software driver to initiate network traffic redistribution among the remaining reliable NICs in the computing device. Using this hash engine, the software driver is able to intelligently redirect each of the network connections on an unreliable NIC to a reliable NIC within the computing device, in a way that optimizes the distribution of network traffic across the remaining reliable NICs. Alternatively, if a connection is moved from an old NIC to a new NIC, the software driver can detect the moved connection and offload the moved connection to a hardware offload engine on the new NIC. With this approach, issues such as network interface overloading and computing device performance degradation may be more easily avoided when failing over network connections, thereby improving overall system performance relative to prior art techniques. | 11-20-2008 |
| 20080285552 | INTELLIGENT FAILOVER IN A LOAD-BALANCED NETWORKING ENVIRONMENT - A hash table in the network device driver maintains data on the traffic characteristics for each network interface (“NIC”) within a computing device. If one of the NICs in the computing device becomes unreliable, the cost function in the hash engine allows the software driver to initiate network traffic redistribution among the remaining reliable NICs in the computing device. Using this hash engine, the software driver is able to intelligently redirect each of the network connections on an unreliable NIC to a reliable NIC within the computing device, in a way that optimizes the distribution of network traffic across the remaining reliable NICs. Alternatively, if a connection is moved from an old NIC to a new NIC, the software driver can detect the moved connection and offload the moved connection to a hardware offload engine on the new NIC. With this approach, issues such as network interface overloading and computing device performance degradation may be more easily avoided when failing over network connections, thereby improving overall system performance relative to prior art techniques. | 11-20-2008 |
| 20080285553 | INTELLIGENT LOAD BALANCING AND FAILOVER OF NETWORK TRAFFIC - A hash engine in a network device driver maintains data on the utilization and error rate for each network interface card (“NIC”) within a local computing device. From this data, the hash engine intelligently selects transmit NICs and receive NICs based on various networking parameters provided from a software driver program. Transmit packets sent from the operating system in a local computing device to a remote computing device are intercepted, modified and redirected to transmit NICs selected by the hash engine for transmission to remote computing devices. Similarly, address resolution protocol (“ARP”) response packets sent by the operating system in response to ARP request packets are intercepted, modified and redirected to receive NICs selected by the hash engine for transmission. By selecting receive NICs and transmit NICs in this fashion, the hash engine is able to intelligently load balance transmit and receive traffic in the local computing device, thereby improving overall network performance relative to prior art techniques. | 11-20-2008 |
Philip Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110194450 | CELL COPY COUNT HAZARD DETECTION - The present invention is directed to a network device, method and apparatus for processing data. The present invention includes at least one ingress module for performing switching functions on incoming data. The invention further includes a memory management unit (MMU) for storing the incoming data, and at least one egress module for transmitting the incoming data to at least one egress port. Further, in the present invention, the memory management unit further comprises a cell copy count pool (CCP) memory, wherein the CCP determines when a memory cell can be made available. | 08-11-2011 |
Philip H. Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090275170 | LOW TEMPERATURE HERMETIC BONDING AT WATER LEVEL AND METHOD OF BONDING FOR MICRO DISPLAY APPLICATION - A spatial light modulator is fabricated by bonding a capping layer over a wafer bearing active reflecting surfaces utilizing a low temperature bonding agent capable of providing a hermetic seal, such as a glass frit. The low temperature bonding agent may be B-stage cured after application to the capping layer, prior to any exposure to the substrate bearing the reflecting surfaces. In accordance with one embodiment of the present invention, the capping layer may comprise a glass wafer pre-bonded with an interposer spacer layer to provide sufficient stand-off between the capping layer and the underlying reflecting structures. In accordance with an alternative embodiment of the present invention, the capping layer may comprise a glass wafer alone, and the bonding agent may include additional materials such as beads or balls to provide the necessary stand-off between the capping layer and the underlying reflective structures. | 11-05-2009 |
Po-Jui Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110192229 | MICRO ELECTRICAL MECHANICAL MAGNETIC FIELD SENSOR UTILIZING MODIFIED INERTIAL ELEMENTS - A micro electrical-mechanical system (MEMS) is disclosed. The MEMS includes a substrate, a first pivot extending upwardly from the substrate, a first lever arm with a first longitudinal axis extending above the substrate and pivotably mounted to the first pivot for pivoting about a first pivot axis, a first capacitor layer formed on the substrate at a location beneath a first capacitor portion of the first lever arm, a second capacitor layer formed on the substrate at a location beneath a second capacitor portion of the first lever arm, wherein the first pivot supports the first lever arm at a location between the first capacitor portion and the second capacitor portion along the first longitudinal axis, and a first conductor member extending across the first longitudinal axis and spaced apart from the first pivot axis. | 08-11-2011 |
Qiming Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100235176 | DYNAMIC INTERFACE BETWEEN BPSS CONVERSATION MANAGEMENT AND LOCAL BUSINESS MANAGEMENT - The present invention relates to devices and methods that coordinate an external conversation process between entities with an internal workflow of one of the entities. More particularly, it relates to devices and methods that are compliant with an inter-enterprise conversation process standard for routing electronic commerce documents between enterprises. Particular aspects of the present invention are described in the claims, specification and drawings. | 09-16-2010 |
Sean Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090184904 | System and Method for Backlight Control for An Electronic Display - The present invention discloses apparatus and techniques relating to the intelligent control of a display's backlight LED strings. The present invention provides for controlling the display intensity on a region-by-region basis and for adjusting the intensity multiple times within the duration of a frame. The present invention also provides backlight adjustment in a manner that emphasizes certain colors and deemphasizes certain colors. The present invention also provides for adjustment of the backlight based on the ambient temperature. | 07-23-2009 |
| 20100333161 | SYSTEM AND METHOD FOR RECORDING AND TIME-SHIFTING PROGRAMMING IN A TELEVISION DISTRIBUTION SYSTEM WITH LIMITED CONTENT RETENTION - Various embodiments of the disclosed subject matter provide methods and systems to record broadcast programming for at least one television channel for a period of time, wherein the recording is performed upstream from subscribers in a television distribution system, and further including after the period of time, keeping recorded programming by request from at least one subscriber. And further wherein the request is for at least one television program contained in the recorded programming or for a time window for a particular channel. According to another embodiment a subscriber requests that broadcast programming be saved for the subscriber upstream from the subscriber in a television distribution system, and wherein the subscriber may request the programming be saved for later viewing by the subscriber between the time the programming was broadcast and a later point in time. | 12-30-2010 |
| 20110012609 | METHOD AND APPARTUS FOR SUB-ASSEMBLY ERROR DETECTION IN HIGH VOLTAGE ANALOG CIRCUITS AND PINS - The innovation relates to systems and/or methodologies for error detection during sub-assembly in high voltage analog circuits. A signal driver communicates test signals to one or more high voltage analog circuits, and a state machine compares the electrical and/or thermal responses of the high voltage analog circuits to a set of predetermined expected results (e.g., signatures). The signal driver and state machine can be incorporated into the high voltage analog circuits. The expected results can be stored in the target circuits in the form of look-up tables, matrices, and so forth. Errors, such as, dry solders and bridge solders can be determined based on the comparison of the obtained responses to the expected signatures. | 01-20-2011 |
Sharline Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090142349 | CD19 Antibodies And Their uses - The present disclosure provides isolated monoclonal antibodies, particularly human monoclonal antibodies that specifically bind to CD19 with high affinity. Nucleic acid molecules encoding such CD19 antibodies, expression vectors, host cells and methods for expressing the CD19 antibodies are also provided. Immunoconjugates, bispecific molecules and pharmaceutical compositions comprising the CD19 antibodies are also provided. Methods for detecting CD19, as well as methods for treating various B cell malignancies, including non-Hodgkin's lymphoma, are disclosed. | 06-04-2009 |
Tania Sung-Yi Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100246551 | Performance optimization for wireless networks with mixed modulation types - In one embodiment, different physical layer standards are segregated into different frequency channels. In one implementation, 802.11b traffic and 802.11g traffic are segregated into different frequency channels. A network management tool allows the user to specify channels to either, e.g., 802.11b-only, 802.11g-only, 802.11b preferred and 802.11g discouraged, or 802.11g preferred and 802.11b discouraged. Access points are given the capability of preventing or discouraging client traffic of either given type. | 09-30-2010 |
We-Hsiung Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090324023 | Combined Face Detection and Background Registration - Techniques are provided to analyze video frames of a video signal in order to distinguish regions containing a face (and body torso) from regions that contain a relatively static background. The region containing the face is referred to as a foreground region. A current video frame is divided into a plurality of elements and the foreground regions and background regions are detected. The background regions of a subsequent video frame are detected/registered using the foreground regions of the current video frame. The foreground regions of the subsequent video frame are determined using the background regions of the current video frame as a temporal reference. | 12-31-2009 |
Wei-Hsiang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080270774 | Universal branch identifier for invalidation of speculative instructions - A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path. | 10-30-2008 |
Xiangrong Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110091098 | System and Method for Detecting Text in Real-World Color Images - A method and apparatus for detecting text in real-world images comprises calculating a cascade of classifiers, the cascade comprising a plurality of stages, each stage including one or more weak classifiers, the plurality of stages organized to start out with classifiers that are most useful for ruling out non-text regions, and removing regions classified as non-text regions from the cascade prior to completion of the cascade, to further speed up processing. | 04-21-2011 |
Xiaopeng Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080267327 | Nonlinear echo compensator for class B transmitter line driver - A nonlinear echo compensator comprises a mapping circuit that includes a weighting circuit that generates a weighted signal based on a current symbol and a prior symbol and a function generating circuit that selects one of N functions based on the weighted signal, where N is an integer greater than one. The mapping circuit generates a driving signal based on the selected one of the N functions and the weighted signal. A canceling circuit generates a nonlinear echo compensation signal based on the driving signal. | 10-30-2008 |
Yen-Kuang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090034609 | METHOD AND APPARATUS FOR PROVIDING PREDICTION MODE FINE GRANULARITY SCALABILITY - In an encoding process, video data are represented as a bitstream of a quantized base layer and at least two enhancement layers, with each picture in each layer identified by a start code. The base layer, plus a number of enhancement layers capable of being transmitted by the communication channel's bandwidth, are transmitted on the communication channel. | 02-05-2009 |
Yih-Chuan Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090161693 | METHOD AND SYSTEM FOR PROGRAMMABLE BANDWIDTH ALLOCATION - The disclosed systems and methods relate to allocating bandwidth to a plurality of ports that access a shared resource. An exemplary system may comprise a multiplexer, a table, and a scheduling circuit. The table may define when a port has access to the shared resource. The table entries may be based on the number of ports with access to the shared resource and the required bandwidth in each of the ports. The scheduling circuit controls the multiplexer according to the table, and the ports may gain access to the shared resource one port at a time. | 06-25-2009 |
Yuan Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110106501 | AUTOMATED DESIGN OF AN IT INFRASTRUCTURE - A method for automated design of an IT infrastructure, includes a) identifying IT equipment to support services to be provided to meet one or more user requirements; b) identifying one or more auxiliary infrastructures to meet requirements of the identified computer equipment; c) synthesizing the IT equipment and the one or more auxiliary infrastructures to generate a candidate design; d) analyzing one or more operating characteristics of the candidate design; e) repeating steps a)-d) on at least one additional candidate design that differs from the candidate design generated at step c); and f) storing at least one of the candidate design and the at least one additional candidate design. | 05-05-2011 |
Yupeng Chen, Sunnyvale, CA US
Zhenfang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090230088 | FORMING A PRINT HEAD WITH A THIN MEMBRANE - A microfabricated device and method for forming a microfabricated device are described. A thin membrane including silicon is formed on a silicon body by bonding a silicon-on-insulator substrate to a silicon substrate. The handle and insulator layers of the silicon-on-insulator substrate are removed, leaving a thin membrane of silicon bonded to a silicon body such that no intervening layer of insulator material remains between the membrane and the body. A piezoelectric layer is bonded to the membrane. | 09-17-2009 |
| 20110092049 | METHOD AND APPARATUS FOR SUBSTRATE BONDING - Methods for bonding a first substrate to a second substrate are described. A surface of the first substrate is coated with an adhesive layer. The adhesive layer is cured to b-stage. The surface of the first substrate is positioned in contact with the second substrate. An edge of the first substrate is pressed to an edge of the second substrate to initiate Van der Waals bonding. The first and second substrates are allowed to come together by Van der Waals bonding. The bonded first and second substrates are subjected to a sufficient heat for a sufficient time period to cure completely the adhesive layer. | 04-21-2011 |
| 20110109694 | Thermal Oxide Coating On A Fluid Ejector - A fluid ejection module includes a flow-path body, a first oxide layer, a membrane, and a second oxide layer. The flow-path body has a first outer surface and an opposing second outer surface and a plurality of flow paths, each flow path extending at least from the first outer surface to the second outer surface. The first oxide layer coats at least an interior surface of each of the flow paths and the first and second outer surfaces of the flow-path body and has a thickness that varies by less than 5% along {100} planes. The membrane has a first outer surface. The second oxide layer is coated on the first outer surface of the membrane and has a thickness that varies by less than 5% along {100} planes and is bonded to the first oxide layer. | 05-12-2011 |
| 20110115341 | Insulated Film Use in a Mems Device - A method of forming an actuator and an actuable device formed by this method are disclosed. This method includes depositing a photoimageable material to form a first photoimageable layer on a piezoelectric layer; patterning the first photoimageable layer to form an aperture; and disposing a first conductive layer on the first photoimageable layer. The first conductive layer partially overlies the first photoimageable layer such that a first portion of the first conductive layer contacts the first photoimageable layer and a second portion of the first conductive layer electrically contacts the piezoelectric layer in the aperture. | 05-19-2011 |
| 20110168317 | Controlled Bond Wave Over Patterned Wafer - A method of bonding two substrates includes placing a separating member between a first substrate and a second substrate, applying pressure to the first substrate to initiate a bond wave between the first substrate and the second substrates with the separating member between the first substrate and the second substrate, and controlling movement of the bond wave by translating the separating member away from a center of the first substrate or the second substrate. | 07-14-2011 |
Zhongqiang Chen, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100011124 | SYSTEMS AND METHODS FOR DETECTING AND PREVENTING FLOODING ATTACKS IN A NETWORK ENVIRONMENT - A method for processing network traffic data includes receiving a packet, and determining whether the packet is a previously dropped packet that is being retransmitted. A method for processing network traffic content includes receiving a plurality of headers, the plurality of headers having respective first field values, and determining whether the first field values of the respective headers form a first prescribed pattern. A method for processing network traffic content includes receiving a plurality of packets, and determining an existence of a flooding attack without tracking each of the plurality of packets with a SYN bit. | 01-14-2010 |
| 20100122344 | SYSTEMS AND METHODS FOR DETECTING AND PREVENTING FLOODING ATTACKS IN A NETWORK ENVIRONMENT - A method for processing network traffic data includes receiving a packet, and determining whether the packet is a previously dropped packet that is being retransmitted. A method for processing network traffic content includes receiving a plurality of headers, the plurality of headers having respective first field values, and determining whether the first field values of the respective headers form a first prescribed pattern. A method for processing network traffic content includes receiving a plurality of packets, and determining an existence of a flooding attack without tracking each of the plurality of packets with a SYN bit. | 05-13-2010 |