Patent application number | Description | Published |
20100219504 | Four-Terminal Gate-Controlled LVBJTs - An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip. | 09-02-2010 |
20110193658 | FILTER USING A WAVEGUIDE STRUCTURE - A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports. | 08-11-2011 |
20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 08-25-2011 |
20120043590 | Linear-Cap Varactor Structures for High-Linearity Applications - A device includes a well region over a substrate, and a heavily doped well region over the well region, wherein the well region and the heavily doped well region are of a same conductivity type. A gate dielectric is formed on a top surface of the heavily doped well region. A gate electrode is formed over the gate dielectric. A source region and a drain region are formed on opposite sides of the heavily doped well region. The source region and the drain region have bottom surfaces contacting the well region, and wherein the source region and the drain region are of opposite conductivity types. | 02-23-2012 |
20120074515 | Noise Decoupling Structure with Through-Substrate Vias - A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. | 03-29-2012 |
20120104387 | Four-Terminal Metal-Over-Metal Capacitor Design Kit - A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer. | 05-03-2012 |
20120187494 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 07-26-2012 |
20120293191 | HVMOS Reliability Evaluation using Bulk Resistances as Indices - A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance. | 11-22-2012 |
20120319176 | GATED-VARACTORS - In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region. | 12-20-2012 |
20130175655 | DUAL DNW ISOLATION STRUCTURE FOR REDUCING RF NOISE ON HIGH VOLTAGE SEMICONDUCTOR DEVICES - An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to V | 07-11-2013 |
20130200489 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors. | 08-08-2013 |
20130260486 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 10-03-2013 |
20130299919 | MOS Devices with Mask Layers and Methods for Forming the Same - A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask. | 11-14-2013 |
20140001518 | Integrated Circuit Devices with Well Regions and Methods for Forming the Same | 01-02-2014 |
20140183660 | POWER CELL AND POWER CELL CIRCUIT FOR A POWER AMPLIFIER - A power cell includes a fin over a substrate, the fin extending in a direction substantially perpendicular to a bottom surface of the substrate. The fin includes a first dopant type. The power cell further includes at least one isolation region over the substrate between the fin and an adjacent fin. The power cell further includes a gate structure in contact with the fin and the at least one isolation region, wherein the gate structure comprises a doped region in the fin, wherein the doped region has a second dopant type different from the first dopant type and the doped region defines a channel region in the fin. | 07-03-2014 |
20140239364 | MOS Varactor Optimized Layout and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 08-28-2014 |
20140264635 | RF Switch on High Resistive Substrate - A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. | 09-18-2014 |
20140291806 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays. A semiconductor device is formed including a capacitor array formed in a plurality of cells in a two-dimensional grid. The capacitor array includes a plurality of operational capacitors formed in a first subset of the plurality of cells along a diagonal of the capacitor array. A first operational capacitor is formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The capacitor array also includes a plurality of dummy patterns formed about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. Each one of the plurality of operational capacitors is electrically coupled to another one of the plurality of operational capacitors. | 10-02-2014 |
20140295640 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors. | 10-02-2014 |
20140332857 | JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET), SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions. | 11-13-2014 |
20140332858 | JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET), SEMICONDUCTOR DEVICE HAVING JFET AND METHOD OF MANUFACTURING - A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions. | 11-13-2014 |
20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
20150021676 | HIGH VOLTAGE METAL-OXIDE-METAL (HV-MOM) DEVICE, HV-MOM LAYOUT AND METHOD OF MAKING THE HV-MOM DEVICE - A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor. | 01-22-2015 |
20150104925 | Noise Decoupling Structure with Through-Substrate Vias - A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. | 04-16-2015 |
20150108581 | FINFET HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME - A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure. | 04-23-2015 |
20150108582 | FINFET HAVING DOPED REGION AND METHOD OF FORMING THE SAME - A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure. | 04-23-2015 |
20150228725 | Buried-Channel FinFET Device and Method - A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. The fins are doped to form source, drain and buried channel regions. A gate stack is formed over the buried channel regions. Contacts are formed to provide electrical contacts to the source/drain regions and the gate. | 08-13-2015 |
Patent application number | Description | Published |
20100125994 | INTERFACE CARD FIXING DEVICE - An interface card fixing device that is installed within a computer case, and is provided with a plurality of sets of push rods, which an assembler can move using his hand to cause the push rods to hold down the L-shaped installation pieces of interface cards. Application of pressure to these installation pieces is used to complete quick fixation of the interface cards to corresponding positions of the interior of the computer case, and the assembler does not need to use any hand tools to complete assembly or disassembly of the interface card. | 05-27-2010 |
20100132979 | WIRE KEEPER - A wire keeper is assembled in a computer case to guide, integrate and fix wires of plural bus lines and electric connecting cords which are layout in the case, allowing each wire in the case to be tidily collected to assure space in the case to keep clear properly. As a result, hot air in the case can be transmitted out successfully by a cooling fan to effectively improve a heat dissipation effect in the case. | 06-03-2010 |
20100301181 | POWER SUPPLY FIXING DEVICE - A power supply fixing device can effectively fix a power supply inside a computer case. One end of the power supply fixing device is movably assembled at a plate in the computer case, and a suppress surface is used to suppress the power supply. In addition, by hooking at the other end, which is formed at the fixing device, to the other plane of the computer case, and by moving an operating member of the fixing device to a packing position, the entire power supply can be fixed. The entire operation process is performed without an aid of a hand tool, and there is no need to use screws or screw holes, such that the power supply can be dismantled and assembled more conveniently. | 12-02-2010 |
20110064536 | Electronic component fixing device - An electronic component fixing device, which includes the restraining piece positioned in a horizontal direction to an electronic component, and at least one antiskid screw positioned in a vertical direction to the electronic component. When installing the electronic component, the restraining piece is assembled to a retaining wall of a computer case, and the antiskid screws are caused to movable penetrate a partition of the computer case, thereby separately restraining the horizontal surface and the perpendicular surface of the electronic component so as to suppress vibration in a horizontal direction and vertical direction of the electronic component when operating, and reduce noise produced by friction or impact with the computer case. | 03-17-2011 |
20110090642 | Heat Dissipation Device - A heat dissipation device which is assembled in a computer case is primarily constituted by a cooling fan, a circuit drive unit, an MCU (Microcontroller Unit) chip and a light emitting unit. The MCU chip is used to detect a power load of a power supply, and the circuit drive unit is used to drive the light emitting unit to produce a change of various light colors, according to a result of detection; this allows a user to identify a power load and output of the power supply by watching directly. | 04-21-2011 |
20110255235 | Disk Drive Case - A disk drive case is used to hold a disk drive and is then assembled into a corresponding slot in a computer case. The disk drive case provides a carrier to effectively protect the disk drive, allowing the disk drive to be quickly inserted into and pulled out of the slot of the computer case, such that the computer assembly operation can be faster and more convenient. | 10-20-2011 |
20120093638 | Plug-In Fan - A plug-in fan is assembled at a periphery of an electronic device. By an operation of the plug-in fan, temperature resulted when the electronic device is operating is decreased. An assembly plane of the periphery of the electronic device is formed with a plurality of plug-in holes, and corresponding assembly planes of the plug-in fan are assembled with a plurality of corresponding plug-in devices. When they are assembled correspondingly, each plug-in device corresponds with each plug-in hole and both are fixed quickly by pushing in or latching in. In addition, the assembling can be quickly accomplished without requiring an assistance of any hand tool. | 04-19-2012 |
Patent application number | Description | Published |
20090151966 | Switching Device For Impact Power Tool - A switching device for an impact power tool includes an input unit, a clutch unit, an output unit and a spring. The clutch unit is cooperated with the spring and located between the input unit and the output unit. The clutch unit includes a clutch disc connected to an input shaft of the input unit and a collar. The output unit includes an output shaft with struck blocks and a pounding member with striking blocks. When the collar is moved and connected with the clutch disc, the input shaft, the pounding member, the collar and the output shaft rotate simultaneously. The output shaft outputs rotation only. When the collar is moved and disengaged from the clutch disc, the input shaft drives the pounding member and the pounding member drives the output shaft to rotate. The output shaft outputs rotation with impact intermittently. | 06-18-2009 |
20090169336 | Locking Device With Quick Release Mechanism - A locking device includes an outer ring in which a clutch disc and a locking disc are respectively connected at two opposite sides thereof A first pad is located on clutch disc and a second pad is located on the first pad. A plurality of balls are located between adjacent first and second protrusions of the first and second pads. A plurality of springs are biased between the far first and second protrusions. A screw bolt connected with a grinding wheel is threadedly extended through the locking disc. When the outer ring is rotated in first direction, the balls do not fall into the recesses defined in the locking disc so as to push the clutch disc to lock the grinding wheel. When the outer ring is rotated in second direction, the balls fall into the recesses and the clutch disc is loosened from the grinding wheel. | 07-02-2009 |
20090277291 | Power Output Mechanism For Power Tools - A power output mechanism for power tools includes a main part for driving an output shaft, a switch unit, an impact unit, a pressing unit, and an operation member. The switch unit has a rotation collar for controlling positions of positioning springs. The impact unit includes an orientation wheel movably connected to the output shaft and an operation wheel secured to the output shaft. The orientation wheel includes a first toothed contact surface which is removably engaged with a second toothed contact surface of the operation wheel. A corrugated ring portion is defined on an outer periphery of the orientation wheel and limited from rotation relative to the output shaft when the positioning springs are moved to certain positions. When the positioning springs are engaged with the orientation wheel, the orientation wheel cannot freely rotate relative to the output shaft so that an impact is output. | 11-12-2009 |
20100319945 | OUTPUT MODE SWITCHING APPARATUS - An output mode switching apparatus including a power unit, a hammering unit, an output shaft, a housing, and a shifting member is provided. The hammering unit includes a gasket cup, a switching ring, a spring member, a hammering seat, and a main shaft. When the power unit is not in operation, the switching ring is restricted so as to be positioned against and secured to the gasket cup. When the mains shaft is driven by the power unit to rotate, the hammering seat is carried to rotate and is applied with a restriction for restricting the hammering seat from axial movement, thus configuring an output mode of electric drill. When the shifting member is turned, the restriction applied to the hammering seat is released. The hammering blocks repetitively hammers the protrusion blocks and axially returns back to the original position, thus configuring an impact output mode. | 12-23-2010 |
20110030984 | MAIN SHAFT LOCKING MECHANISM - A main shaft locking mechanism includes a fixing ring, a main shaft and detents. The main shaft includes an equilateral portion that has an equilateral cross section. A number of the corners of the equilateral portion is equal to that of the detents. The detent has an exterior side and an interior side opposite to the exterior side. The interior side includes two corner protrusions protruded out from two ends thereof and a concave portion defined between the two corner protrusions. The corners of the main shaft are received in the concave portions of the detents. When the main shaft is manually driven to rotate, the corners of the main shaft drive the detents to deviate. Therefore, the exterior sides of the detents interfere against the fixing ring. Then the detents prevent the main shaft from further rotating, thus locking up the main shaft. | 02-10-2011 |
20110053728 | MULTI-GEAR MECHANISM FOR POWER TOOLS - A multi-gear mechanism includes first and second gear sets, an output set, multiple first planet gears pivotably connected between the first and second gear sets, a first gear ring having internal teeth and external teeth, multiple second planet gears cooperated with the internal teeth of the first gear ring, a second gear ring having internal teeth and side teeth, an operation gear ring and a motor gear. The motor gear extends through two central holes of the first and second gear sets, and the first and second planet gears are engaged with the motor gear. The operation gear ring is connected with the second gear ring which drives the operation gear ring to move axially. The motor gear drives the output set at low speed, constant speed or high speed when the operation gear ring and the second gear ring are operated to engage with different gears. | 03-03-2011 |
20110278133 | GAPLESS MAIN SHAFT LOCKING APPARATUS - A gapless main shaft locking apparatus includes a fastening ring, an elastic retaining device, a plurality of detent pins, a driving plate and an output shaft. The elastic retaining device is installed in the fastening ring and has an inner space in which elastic portions and cylinder portions are disposed. Each of the detent pins is disposed between one of the elastic portions and one of the cylinder portions. The driving plate has a central hole, and the periphery of the central hole includes fan-shaped convex portions. A side of the driving plate has a plurality of concave slots for receiving the elastic retaining device. The output shaft includes a polygonal shaft having a regular polygonal cross section. The polygonal shaft passes through the central hole of the driving plate, and each side of the polygonal shaft is contacted with one of the detent pins. | 11-17-2011 |
20130072341 | MULTI-SPEED GEAR SYSTEM FOR POWER TOOL - A multi-speed gear system for a power tool includes a case, a lever, a gear disk, a movable member, a ring gear, a planet gear unit and an idle gear unit. The movable member is axially moved to be engaged with the ring gear, the planet gear unit or the idle gear unit to change the gear ratios and output different speeds. The parts that are engaged with the movable member are located outside of the area where the gears are located, so that the switching between the speeds is smooth and has less friction. | 03-21-2013 |
20130213680 | POWER TOOL HAVING VARIABLE SPEED DEVICE - A power tool includes a variable speed device which can be set in an auto mode or a manual mode. The power tool does not need the user to set the speed when it is operated at the auto mode. The power tool is reset to be the high-speed mode when it is activated. The speed is reduced along with the working load so as to output high torque, maintain the best working efficiency and protect the power tool under the operative status. The power tool can be set to the manual mode so as to work in a single type of function. | 08-22-2013 |