| Patent application number | Description | Published |
|---|
| 20090096462 | Wafer testing method - A wafer testing method for wafer testing system comprises the steps: loading a wafer and then positioning the wafer relatively to a map file image stored in a map file. The map file is of a first file type. The next step is inspecting the appearance of the wafer. When the user detects defects on the wafer, the positions of the defects are directly recorded in the map file and then the modified map file is saved. The map file can be directly modified when the wafer is in the testing procedure so that the testing time is reduced. Furthermore, the precision of the testing is improved. | 04-16-2009 |
| 20090251815 | Testing system and testing method for inspecting electonic devices - A testing system for inspecting electronic devices includes a first transparent disk, a first image capturing unit disposed under the first transparent disk, a second disk disposed next to the first transparent disk, a guiding unit disposed on adjacent area between the transparent disk and the second disk, and a plurality of second image capturing units disposed around the second disk. A plurality of electronic devices is continuingly supplied onto the first transparent disk and the first image capturing unit is used for capturing the images of the bottom surfaces of the electronic devices. Then, the electronic devices are guided to the second disk via the guiding unit and the second image capturing units are used for capturing the images of other surfaces of the electronic devices. A testing method for electronic devices is further disclosed. | 10-08-2009 |
| 20100166290 | DIE DEFECT INSPECTING SYSTEM WITH A DIE DEFECT INSPECTING FUNCTION AND A METHOD OF USING THE SAME - A die defect inspecting system with a die defect inspecting function includes a wafer-positioning module, an image-capturing module, a die-sucking module, a die defect analyzing module, a die-classifying module and a control module. The image-capturing module is disposed beside one side of the wafer-positioning module in order to capture an image of each die. The die-sucking module is disposed above the wafer-positioning module and the image-capturing module in order to suck each die from the wafer-positioning module to a position above the image-capturing module for capturing a back image of a back surface of each die. The die defect analyzing module is electrically connected to the image-capturing module in order to judge whether the back image of the back surface of each die passes inspection standard. | 07-01-2010 |
| Patent application number | Description | Published |
|---|
| 20090014704 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 01-15-2009 |
| 20100193763 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 08-05-2010 |
| 20120016472 | Color Tactile Vision System - A tactile display writer unit includes a probe having a contact tip, and at least a first actuator and a second actuator coupled to the probe, whereby activation of the actuators results in a displacement of the probe tip in one or more of a z-direction and in a lateral direction having a vector in an x-y plane. Also, a display writer includes a plurality of such units supported in an x-y array. The writer units may have a third actuator coupled to the probe. Also, a tactile vision system includes such a display writer, an image processor, and an image sensor. The processor transforms RGB image information from the image sensor into hue-based information having two or more attributes; and the actuators in the tactile display writer are activated by the information attributes. Also, a method for producing a tactile color stimulus at a site on the skin of a subject includes providing a probe having a contact tip; displacing the tip at the contact site in a direction generally normal to the skin surface at the site to an extent that relates one attribute of a hue-based model of the color, and displacing the tip in at least one lateral direction generally in a plane parallel to the skin surface at the site to an extent that relates to at least one additional attribute of the color. | 01-19-2012 |
