| Patent application number | Description | Published |
|---|
| 20080203996 | System and method for monitoring negative bias in integrated circuits - A bias voltage monitoring circuit is disclosed which comprises a first device coupled between a positive high voltage power supply (VDD) and a first node, a second device coupled between the first node and a second node where the bias voltage is applied, and a pad coupled to the first node, wherein the first and second devices form a voltage divider and a voltage measured at the pad reflects the bias voltage, and the first device and the second device is so chosen that a voltage at the first node is always positive for a given range of the bias voltage. | 08-28-2008 |
| 20080225616 | METHOD FOR INCREASING RETENTION TIME IN DRAM - The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation. | 09-18-2008 |
| 20080225617 | METHOD FOR HIGH SPEED SENSING FOR EXTRA LOW VOLTAGE DRAM - A method and apparatus are provided for sensing in low voltage DRAM memory cells. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first and second NMOS transistor, each having a source and a first and second PMOS transistor, each having a source. The method further includes the steps of maintaining the voltage of the sources of the first and second NMOS transistors at a first voltage during normal operation and lowering the voltage of the sources of the first and second NMOS transistors from the first voltage to a second voltage during a read operation. | 09-18-2008 |
| 20090021234 | Ultra low-voltage sub-bandgap voltage reference generator - A low-voltage sub-bandgap reference circuit is disclosed. In one embodiment, the low-voltage sub-bandgap voltage reference circuit includes a differential amplifier and a first bipolar transistor with its base and collector coupled to an electrical ground. The reference circuit further includes a second bipolar transistor with base and collector coupled to the electrical ground. The reference circuit further includes a DC bias circuit supplying a predetermined voltage output between a high and low voltage terminal, the high voltage terminal being coupled to both collectors of the first and second bipolar transistors and the low voltage terminal being coupled to both bases of the first and second bipolar transistors. | 01-22-2009 |
