Patent application number | Description | Published |
20080197461 | Apparatus for wire bonding and integrated circuit chip package - An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided. | 08-21-2008 |
20080242019 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate. A gate dielectric layer is formed on the semiconductor substrate. A first conductive layer is formed on the gate dielectric layer, wherein the first conductive layer is an in-situ doped conductive layer. A second conductive layer is formed on the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a gate electrode. | 10-02-2008 |
20080299754 | Methods for forming MOS devices with metal-inserted polysilicon gate stack - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer. | 12-04-2008 |
20080305646 | Atomic layer deposition - An atomic layer deposition with hydroxylation pre-treatment is provided. The atomic layer deposition comprises the steps of (a) performing a hydroxylation pre-treatment on a silicon substrate to create a predetermined number of hydroxyl groups thereon; (b) performing a precursor pulse on the pre-treated silicon substrate, wherein the precursor react with the hydroxyl groups, forming a layer; (c) purging the silicon substrate with an inert carrier gas; (d) performing a water pulse on the layer sufficiently so as to create a predetermined number of hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b)˜(e) until the atomic layer deposition is completed. Each layer overlying the silicon substrate has a minimum of 70 percent surface hydroxyl groups. | 12-11-2008 |
20100151639 | METHOD FOR MAKING A THERMALLY-STABLE SILICIDE - Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively. | 06-17-2010 |
20100155849 | TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MC | 06-24-2010 |
20100244247 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer. | 09-30-2010 |
20100258870 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap. | 10-14-2010 |
20100279515 | ATOMIC LAYER DEPOSITION - A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer. | 11-04-2010 |
20100330788 | THIN WAFER HANDLING STRUCTURE AND METHOD - A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer. | 12-30-2010 |
20110001250 | METHOD AND STRUCTURE FOR ADHESION OF INTERMETALLIC COMPOUND (IMC) ON CU PILLAR BUMP - A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer. | 01-06-2011 |
20110027944 | METHOD OF FORMING ELECTRICAL CONNECTIONS - A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material. | 02-03-2011 |
20110049705 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer. | 03-03-2011 |
20110108922 | INTEGRATED CIRCUITS INCLUDING METAL GATES AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process. | 05-12-2011 |
20110198747 | CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component formed on a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface. The semiconductor substrate includes a plurality of devices on the first surface. A plurality of through silicon vias (TSVs) in the semiconductor substrate extends from the first surface to the second surface. A protection layer overlies the devices on the first surface of the semiconductor substrate. A plurality of active conductive pillars on the protection layer have a first height. Each of the active conductive pillars is electrically connected to at least one of the plurality of devices. A plurality of dummy conductive pillars on the protection layer have a second height. Each of the dummy conductive pillars is electrically isolated from the plurality of devices. The first height and the second height are substantially equal. | 08-18-2011 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20110260317 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer. | 10-27-2011 |
20110285005 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure. | 11-24-2011 |
20110291288 | PACKAGE SYSTEMS HAVING INTERPOSERS - A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure. | 12-01-2011 |
20120007132 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time. | 01-12-2012 |
20120061059 | COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid. | 03-15-2012 |
20120063090 | COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - An apparatus for cooling a stacked die package comprises a substrate, a first die above the substrate, a second die above the first die, and a housing containing the first and second dies. The housing seals the first and second dies from the environment. The apparatus further includes a cooling fluid in fluid communication with the first die and the second die to transfer the heat from the dies to the housing. | 03-15-2012 |
20120074582 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 03-29-2012 |
20130049194 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A semiconductor device including a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. A method of forming a semiconductor device. The method includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn). | 02-28-2013 |
20130059443 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface. | 03-07-2013 |
20130062767 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall. | 03-14-2013 |
20130149856 | Interface Structure for Copper-Copper Peeling Integrity - An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface. | 06-13-2013 |
20130270700 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. | 10-17-2013 |
20130295762 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer. | 11-07-2013 |
20130299972 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A semiconductor device includes a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. The semiconductor device further includes a cap layer over a top surface of the conductive post. A method of forming a semiconductor device includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn). The method further includes forming a cap layer on a top surface of the conductive post. | 11-14-2013 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20130323883 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 12-05-2013 |
20140077309 | INTEGRATED CIRCUITS INCLUDING METALLIC GATE LAYERS - An integrated circuit includes an NMOS and a PMOS disposed over a substrate. The NMOS transistor includes a first gate dielectric structure over the substrate, a first work function metallic layer over the first gate dielectric structure, a conductive layer over the first work function metallic layer, and a silicide layer over the conductive layer. The PMOS transistor includes a second gate dielectric structure over the substrate, and a second work function metallic layer over the first gate dielectric structure. The PMOS transistor is devoid of any silicide material on the second work function metallic layer. | 03-20-2014 |
20140103526 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A semiconductor device includes a copper-containing post overlying and electrically connected to a bond pad region. The semiconductor device further includes a protection layer on a surface of the copper-containing post, where the protection layer includes manganese. | 04-17-2014 |