| Patent application number | Description | Published |
|---|
| 20080197461 | Apparatus for wire bonding and integrated circuit chip package - An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided. | 08-21-2008 |
| 20080242019 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate. A gate dielectric layer is formed on the semiconductor substrate. A first conductive layer is formed on the gate dielectric layer, wherein the first conductive layer is an in-situ doped conductive layer. A second conductive layer is formed on the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a gate electrode. | 10-02-2008 |
| 20080299754 | Methods for forming MOS devices with metal-inserted polysilicon gate stack - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer. | 12-04-2008 |
| 20080305646 | Atomic layer deposition - An atomic layer deposition with hydroxylation pre-treatment is provided. The atomic layer deposition comprises the steps of (a) performing a hydroxylation pre-treatment on a silicon substrate to create a predetermined number of hydroxyl groups thereon; (b) performing a precursor pulse on the pre-treated silicon substrate, wherein the precursor react with the hydroxyl groups, forming a layer; (c) purging the silicon substrate with an inert carrier gas; (d) performing a water pulse on the layer sufficiently so as to create a predetermined number of hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b)˜(e) until the atomic layer deposition is completed. Each layer overlying the silicon substrate has a minimum of 70 percent surface hydroxyl groups. | 12-11-2008 |
| 20100151639 | METHOD FOR MAKING A THERMALLY-STABLE SILICIDE - Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively. | 06-17-2010 |
| 20100155849 | TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MC | 06-24-2010 |
| 20100244247 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer. | 09-30-2010 |
| 20100258870 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap. | 10-14-2010 |
| 20100279515 | ATOMIC LAYER DEPOSITION - A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer. | 11-04-2010 |
| 20100330788 | THIN WAFER HANDLING STRUCTURE AND METHOD - A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer. | 12-30-2010 |
| 20110001250 | METHOD AND STRUCTURE FOR ADHESION OF INTERMETALLIC COMPOUND (IMC) ON CU PILLAR BUMP - A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer. | 01-06-2011 |
| 20110027944 | METHOD OF FORMING ELECTRICAL CONNECTIONS - A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material. | 02-03-2011 |
| 20110049705 | SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer. | 03-03-2011 |
| 20110108922 | INTEGRATED CIRCUITS INCLUDING METAL GATES AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit is provided. The method includes forming a gate electrode of an NMOS transistor over a substrate by a gate-first process. A gate electrode of a PMOS transistor is formed over the substrate by a gate-last process. | 05-12-2011 |
