| Patent application number | Description | Published |
|---|
| 20100122229 | Apparatus and Method of Preventing Congestive Placement - An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the pattern generating module generates a redistribution pattern with a density distribution of blockages. The density distribution gradually decreases outward. The placement module regards the congestive region as the center redistributes the blockages and electronic cells according to the redistribution pattern. | 05-13-2010 |
| 20100242009 | Method and Apparatus For Preventing Congestive Placement - A congestive placement preventing apparatus, applied in a logic circuit layout having 2 | 09-23-2010 |
| 20100271066 | CIRCUIT PROTECTING APPARATUS AND ASSOCIATED METHOD, AND CIRCUIT PROTECTING LAYER - A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip. | 10-28-2010 |
| 20100281443 | Change Point Finding Method and Apparatus - A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points. | 11-04-2010 |
| 20100295578 | Clock Tree Distributing Method - A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-dimensional interface arrangement to a one-dimensional interface arrangement according to the conversion rate, forming a one-dimensional clock tree according to the one-dimensional interface arrangement, generating the clock tree corresponding to the two-dimensional interface arrangement by converting the one-dimensional clock tree according to the conversion rate | 11-25-2010 |
| 20110126166 | Apparatus for Preventing Congestive Placement and Associated Method - A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule. | 05-26-2011 |
| 20110153303 | Static IR (voltage) drop Analyzing Apparatus and Associated Method - A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor. | 06-23-2011 |
| 20110219346 | Apparatus and Method for preventing Congestive Placement - A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region. | 09-08-2011 |
