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Chen, Fremont
Ben W. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090013165 | PORTABLE USB DEVICE THAT BOOTS A COMPUTER AS A SERVER - Techniques for booting a host computer from a portable storage device with customized settings have been described herein. According to one embodiment, in response to detecting a portable storage device inserted into a first host computer having a first operating environment provided by a first operating system (OS) installed in the first host computer, rebooting the first host computer into a second operating environment using a second OS image stored in the portable device. In addition, a personal configuration file stored in the portable device is extracted to configure the second operating environment of the first host computer, such that the user of the portable storage device can operate the second host computer in view of the personal working environment. Other methods and apparatuses are also described. | 01-08-2009 |
Chao-Peng Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080213691 | Method to print photoresist lines with negative sidewalls - A write pole for vertical magnetic recording is described. It includes a trapezoidal prism of high magnetic moment material, having inwardly sloping sidewalls. Its parallel surfaces are between about 0.1 and 0.3 microns apart and the sidewalls slope in the range of 15.5 to 60 degrees relative to vertical. | 09-04-2008 |
| 20110011744 | Novel method to reduce void formation during trapezoidal write pole plating in perpendicular recording - A method of forming a write pole in a PMR head is disclosed that involves forming an opening in a mold forming layer. A conformal Ru seed layer is formed within the opening and on a top surface. An auxiliary layer made of CoFeNi or alloys thereof is formed as a conformal layer on the seed layer. All or part of the auxiliary layer is removed in an electroplating solution by applying a (−) current or voltage during an activation step that is controlled by activation time. Thereafter, a magnetic material is electroplated with a (+) current to fill the opening and preferably has the same CoFeNi composition as the auxiliary layer. The method avoids Ru oxidation that causes poor adhesion to CoFeNi, and elevated surfactant levels that lead to write pole impurities. Voids in the plated material are significantly reduced by forming a seed layer surface with improved wettability. | 01-20-2011 |
| 20110094888 | Rejuvenation method for ruthenium plating seed - A method of rejuvenating a Ru plating seed layer during write pole fabrication in a PMR head is disclosed that involves forming an opening in a mold forming layer. A Ru seed layer is deposited by CVD within the opening and on a top surface of the mold forming layer. The substrate with the Ru seed layer is immersed in an acidic solution and an electric potential is applied for 1 to 2 minutes such that hydrogen is generated to reduce ruthenium oxides to Ru metal on the seed layer surface in an activation step. One or more surfactants are used to improve wettability of the Ru layer. The substrate is transferred directly to an electroplating solution without drying following the activation step to minimize exposure to oxygen that could regenerate oxides on the surface of the Ru layer. As a result, write pole voids and delamination are significantly reduced. | 04-28-2011 |
Charles C. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080204933 | Granular perpendicular magnetic recording media with multi-interlayer structure - A perpendicular magnetic recording medium comprises a layer stack formed over a surface of a non-magnetic substrate, and comprising, in overlying sequence from the surface: a magnetically soft underlayer; an interlayer structure for crystallographically orienting a layer of a perpendicular magnetic recording material formed thereon; and at least one crystallographically oriented, magnetically hard, perpendicular magnetic recording layer on the interlayer structure; wherein the interlayer structure is a triple-layer stacked structure comprising: a first interlayer of a first non-magnetic material proximal the magnetically soft underlayer and containing Ru; a second interlayer of a second non-magnetic material in overlying contact with the first interlayer and not containing Ru; and a third interlayer of a third non-magnetic material in overlying contact with the second interlayer and containing Ru. | 08-28-2008 |
| 20100209737 | MAGNETIC RECORDING MEDIA WITH ENHANCED WRITABILITY AND THERMAL STABILITY - Aspects are directed to recording media with enhanced magnetic properties for improved writability. Examples can be included or related to methods, systems and components that allow for improved writability while reducing defects so as to obtain uniform magnetic properties such as uniformly high anisotropy and narrow switching field distribution. Some examples include a recording medium with an exchange tuning layer inserted between the hard layer and the soft, semi-soft or thin semi-hard layer so as to maximize the writability improvement of the media. Preferably, the exchange tuning layer is granular and reduces or optimizes the vertical coupling between the hard layer and the soft, semi-soft or semi-hard layer of a magnetic recording or storing device. | 08-19-2010 |
Charles C.y. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100105594 | PROCESS OF PURIFICATION OF AMIDOXIME CONTAINING CLEANING SOLUTIONS AND THEIR USE - The invention relates to processes for producing and using amidoxime compounds with low trace metal impurities. The invention further relates to compositions comprising amidoxime compounds with low trace metal impurities, such compositions useful for cleaning or removing residues from semiconductor substrates and/or equipment. | 04-29-2010 |
Che-Hong Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090082431 | MITOCHONDRIAL ALDEHYDE DEHYDROGENASE-2 MODULATORS AND METHODS OF USE THEREOF - The present invention provides compounds that function as modulators of mitochondrial aldehyde dehydrogenase-2 (ALDH2) activity; and pharmaceutical compositions comprising the compounds. The present invention provides therapeutic methods involving administering a subject compound, or a subject pharmaceutical composition. The present invention further provides assays for identifying agonists of ALDH2. | 03-26-2009 |
| 20090280516 | CRYSTAL STRUCTURE OF ALDEHYDE DEHYDROGENASE AND METHODS OF USE THEREOF - The present disclosure provides a crystal structure of aldehyde dehydrogenase (ALDH) with a modulator of ALDH bound thereto. The present disclosure provides a computer readable medium comprising atomic coordinates for an ALDH polypeptide and a modulator bound to a site within the polypeptide. A method is also provided. In general terms, the method comprises computationally identifying a compound that binds to an ALDH polypeptide, using the atomic coordinates. | 11-12-2009 |
| 20100063100 | MODULATORS OF ALDEHYDE DEHYDROGENASE ACTIVITY AND METHODS OF USE THEREOF - The present invention provides compounds that function as modulators of aldehyde dehydrogenase activity; and pharmaceutical compositions comprising the compounds. The present invention provides therapeutic methods involving administering a subject compound, or a subject pharmaceutical composition. | 03-11-2010 |
| 20100113423 | Modulators of Aldehyde Dehydrogenase and Methods of Use Thereof - The present disclosure provides compounds that function as modulators of aldehyde dehydrogenase (ALDH) enzymatic activity, as well as compositions and formulations comprising the compounds. The present disclosure provides therapeutic methods involving administering a subject compound, or a subject pharmaceutical composition. | 05-06-2010 |
| 20110105602 | Mitochondrial Aldehyde Dehydrogenase-2 Modulators and Methods of Use Thereof - The present invention provides compounds that function as modulators of mitochondrial aldehyde dehydrogenase-2 (ALDH2) activity; and pharmaceutical compositions comprising the compounds. The present invention provides therapeutic methods involving administering a subject compound, or a subject pharmaceutical composition. The present invention further provides assays for identifying agonists of ALDH2. | 05-05-2011 |
Chihhao Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090010655 | Optical communications circuit current management - An optical communications circuit has a communications light signal source and a heat pump coupled to cool the signal source. A controller monitors a current and a temperature of the signal source, and regulates the temperature. The controller updates a heat pump control limit parameter for the heat pump, based on the monitored current. Other embodiments are also described and claimed. | 01-08-2009 |
Ching-Hsuan Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100158247 | METHOD AND SYSTEM FOR SECURE STORAGE, TRANSMISSION AND CONTROL OF CRYPTOGRAPHIC KEYS - A system and method are described supporting secure implementations of 3DES and other strong cryptographic algorithms. A secure key block having control, key, and hash fields safely stores or transmits keys in insecure or hostile environments. The control field provides attribute information such as the manner of using a key, the algorithm to be implemented, the mode of use, and the exportability of the key. A hash algorithm is applied across the key and control for generating a hash field that cryptographically ties the control and key fields together. Improved security is provided because tampering with any portion of the key block results in an invalid key block. The work factor associated with any manner of attack is sufficient to maintain a high level of security consistent with the large keys and strong cryptographic algorithms supported. | 06-24-2010 |
Datong Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080222485 | ERROR CORRECTION METHODS AND APPARATUS FOR MOBILE BROADCAST SERVICES - An apparatus and method of an outer Forward Error Correcting (FEC) code for a mobile broadcast service based on TD-SCDMA network is disclosed. | 09-11-2008 |
| 20080229367 | MOBILE TV BROADCAST SYSTEMS AND METHODS BASED ON TD-SCDMA NETWORK - A mobile TV broadcast system based on TD-SCDMA network is disclosed herein. | 09-18-2008 |
| 20090190547 | NETWORKING METHOD OF SINGLE FREQUENCY NETWORK IN TD-SCDMA SYSTEM - Networking methods of a Single Frequency Network (SFN) in communication systems are disclosed. | 07-30-2009 |
| 20090266354 | SYNCHRONIZED SOLAR CONCENTRATOR ARRAY - A solar energy collecting device includes a rotation axis to be mounted parallel to the earth's polar axis, a solar energy collector mounted for rotation around the rotation axis at a predetermined rotation speed, the solar energy collector defining a tilt angle with respect to the rotation axis, and a tilt angle adjustment mechanism for automatically and intermittently adjusting the tilt angle. Various configurations of the solar energy collector are possible, and the rotation speed may be one revolution per day or half a revolution per day depending on the solar energy collector configuration. Many drive modes are possible, including rotating continuously throughout a day or rotating during daylight hours and rotating backward or forward at night. The tilt angle adjustment mechanism includes a handle fixed to the solar energy collector and a tilt angle change guide. | 10-29-2009 |
| 20100326427 | 1-axis and 2-axis solar trackers - A one-axis sun position tracking device with its rotation axis parallel to the rotation axis of the Earth, rotates perpetually at a constant speed in the opposite direction of the Earth's rotation. This device comprises a shaft that is aligned to the Earth's polar axis, one or more crossbars are rigidly attached to and perpendicular to the shaft, solar energy collectors are mounted on the crossbar and could rotate around the crossbar that defines declination angle. A self-latched declination angle adjustment mechanism keeps the declination angle constant at most of time. A drive mechanism keeps this solar tracker to rotate perpetually. An automatic and abrupt declination angle change will keep the declination angle updated to correct value each day. A similarly configured two-axis tracker that continuously updates its declination angle by a mechanism derived from a differential coaxial rotation. Two independent driving mechanisms control the speed and/or duration of the two coaxial rotations, and are programmed to eliminate all tracking errors from various sources. | 12-30-2010 |
David E-Bin Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100305596 | NON-LINEAR CUT-RATE MULTIPLIER FOR VITREOUS CUTTER - A non-linear cut-rate multiplier for a vitreous cutter is provided whereby a signal from a host drive system may be multiplied in non-linear fashion to achieve significantly higher cut-rates for the vitreous cutter. Depending upon the cut-rate received from the host drive system, the multiplier may be configured to generate a subsequent cut-rate which is, potentially, linear for lower cut-rates of the host drive system and variably non-linear for higher cut-rates of the host drive system. | 12-02-2010 |
David F. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090252309 | SYSTEM AND METHOD FOR AUTHENTICATING A COMMUNICATION DEVICE - A system that incorporates teachings of the present disclosure may include, for example, a communication device having a controller to transmit to a communication system a PKI certificate, and engage in encrypted communications responsive to receiving a public key from the communication system. The communication system can have a plurality of network elements that integrate operations of a circuit-switched communication network and a packet-switched communication network. Other embodiments are disclosed. | 10-08-2009 |
David Fenglin Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100115540 | System and Method to Enable Access to Broadband Services - A provisioning system includes a services management system operable to enable a set-top box device configured to receive broadband services at a first network location to access one or more of the broadband services at a second network location. The first network location is associated with a subscriber account and the second network location is not associated with the subscriber account. The broadband services include a voice service, a data service, and a video service. The provisioning system includes a subscriber authentication system operable to evaluate a request that includes subscriber authorization data, to selectively authorize access to the one or more broadband services at the second network location based on the subscriber authorization data, and to enable the set-top box device to access the one or more broadband services when the set-top box device is at the second network location. | 05-06-2010 |
Diana C. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080218694 | High-resolution Adaptive Optics Scanning Laser Ophthalmoscope with Multiple Deformable Mirrors - An adaptive optics scanning laser opthalmoscopes is introduced to produce non-invasive views of the human retina. The use of dual deformable mirrors improved the dynamic range for correction of the wavefront aberrations compared with the use of the MEMS mirror alone, and improved the quality of the wavefront correction compared with the use of the bimorph mirror alone. The large-stroke bimorph deformable mirror improved the capability for axial sectioning with the confocal imaging system by providing an easier way to move the focus axially through different layers of the retina. | 09-11-2008 |
| 20100149490 | COMPACT ADAPTIVE OPTIC- OPTICAL COHERENCE TOMOGRAPHY SYSTEM - Badal Optometer and rotating cylinders are inserted in the AO-OCT to correct large spectacle aberrations such as myopia, hyperopic and astigmatism for ease of clinical use and reduction. Spherical mirrors in the sets of the telescope are rotated orthogonally to reduce aberrations and beam displacement caused by the scanners. This produces greatly reduced AO registration errors and improved AO performance to enable high order aberration correction in a patient eyes. | 06-17-2010 |
| 20110043917 | DIFFRACTIVE LASER BEAM HOMOGENIZER INCLUDING A PHOTO-ACTIVE MATERIAL AND METHOD OF FABRICATING THE SAME - A method of manufacturing a plurality of diffractive optical elements includes providing a partially transmissive slide, providing a first piece of PTR glass, and directing first UV radiation through the partially transmissive slide to impinge on the first piece of PTR glass. The method also includes exposing predetermined portions of the first piece of PTR glass to the first UV radiation and thermally treating the exposed first piece of PTR glass. The method further includes providing a second piece of PTR glass and directing second UV radiation through the thermally treated first piece of PTR glass to impinge on the second piece of PTR glass. The method additionally includes exposing predetermined portions of the second piece of PTR glass to the second UV radiation, thermally treating the exposed second piece of PTR glass, and repeating providing and processing of the second piece of PTR glass using additional pieces of PTR glass. | 02-24-2011 |
Dongwei Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090256960 | VIDEO TOP-OF-FRAME SIGNAL GENERATOR FOR MULTIPLE VIDEO FORMATS - A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate. | 10-15-2009 |
| 20090256961 | VIDEO CLOCK GENERATOR FOR MULTIPLE VIDEO FORMATS - An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal. | 10-15-2009 |
Dong-Yuan Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080243300 | Object relocation guided by data cache miss profile - Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types. | 10-02-2008 |
Edward Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110156812 | MULTI-BAND, MULTI-MODE RF TRANSMIT AMPLIFIER SYSTEM WITH SEPARATE SIGNAL PATHS FOR LINEAR AND SATURATED OPERATION - A device includes: an input for receiving an RF input signal having a signal format selected among a plurality of signal formats, including at least one signal format to be linearly amplified, and at least another signal format be amplified in saturation; at least a first and a second output; a first amplification path from the input to the first output that includes a first amplifier that operates in a linear amplification mode with respect to the RF input signal; a second amplification path from the input port to the second output that includes the first amplifier, and a second amplifier that operates in saturated amplification with respect to the RF input signal; and a path selection device that selectively passes the RF input signal through the first amplification path or the second amplification path in response to the selected signal format of the RF input signal. | 06-30-2011 |
En-Hsing Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090001615 | SEMICONDUCTOR TEST STRUCTURES - Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds. | 01-01-2009 |
| 20090004879 | TEST STRUCTURE FORMATION IN SEMICONDUCTOR PROCESSING - Test structures are formed during semiconductor processing. The test structures allow performance characteristics to be monitored as the process proceeds. The test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent levels are patterned. The manner of using the mask also allows different types of test structures having different features to be formed. The different types of test structures can provide insight into performance characteristics of different types of devices. | 01-01-2009 |
| 20090004880 | MASK REUSE IN SEMICONDUCTOR PROCESSING - A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers. | 01-01-2009 |
Eric Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080244018 | Personal communication gateway - Disclosed is a method in a personal communication gateway. The method includes communicating with a user terminal through a personal area network interface, accessing multimedia services through a communication network interface, and operating as a proxy to provide for the user terminal access to the multimedia services through the personal area network interface. Also disclosed is a method in a user terminal, which method includes communicating with a personal communication gateway through a personal area network interface, and using the personal communication gateway as a proxy for accessing multimedia services. | 10-02-2008 |
Eric C. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100165383 | LINE UTILIZATION IN INTEGRATED DOCUMENT DELIVERY METHOD AND APPARATUS - A document delivery network server having a set of integrated functions including sending, receiving, routing and filing of FAXes and e-mails to other users which achieves numerous advantages over the prior art. The document delivery system is based on a client/server model having both analog and digital Fax line capabilities. The server side provides very highly integrated systems functionality based on industry standard, commercially available hardware and a mix of industry standard and proprietary software components including integrated FAX/modem modules, an embedded OS, embedded plug-and-play driver sets, embedded e-mail gateways, an embedded FAX archive, embedded back-up/restore, proprietary high efficiency line utilization and highly efficient load balancing. | 07-01-2010 |
| 20110116132 | INTEGRATED DOCUMENT DELIVERY METHOD AND APPARATUS - A document delivery network server having a set of integrated functions including sending, receiving, routing and filing of FAXes and e-mails to other users which achieves numerous advantages over the prior art. The document delivery system is based on a client/server model having both analog and digital Fax line capabilities. The server side provides very highly integrated systems functionality based on industry standard, commercially available hardware and a mix of industry standard and proprietary software components including integrated FAX/modem modules, an embedded OS, embedded plug-and-play driver sets, embedded e-mail gateways, an embedded FAX archive, embedded back-up/restore, proprietary high efficiency line utilization and highly efficient load balancing. | 05-19-2011 |
Eugene Youjun Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080205121 | Current driven memory cells having enhanced current and enhanced current symmetry - A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on. | 08-28-2008 |
| 20090213640 | CURRENT DRIVEN MEMORY CELLS HAVING ENHANCED CURRENT AND ENHANCED CURRENT SYMMETRY - A method and system for providing and using a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each magnetic storage cell includes a magnetic element and a selection device coupled with the magnetic element. The magnetic element is programmed by write currents driven through the magnetic element in a first or second direction. In one aspect, the method and system include providing a voltage supply and a voltage pump coupled with the magnetic storage cells and the voltage supply. The voltage supply provides a supply voltage. The voltage pump provides to the selection device a bias voltage having a magnitude greater than the supply voltage. Another aspect includes providing a silicon on oxide transistor as the selection device. Another aspect includes providing to the body of the transistor a body bias voltage that is a first voltage when the transistor is off and a second voltage when the transistor is on. | 08-27-2009 |
| 20100072524 | Magnetic Devices Having Oxide Antiferromagnetic Layer Next To Free Ferromagnetic Layer - Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low aspect ratios can be fabricated using CMOS processing for, e.g., high-density MRAM memory devices and other devices, using the magnetic biasing layer. Such multilayer structures can be programmed using spin transfer induced switching by driving a write current perpendicular to the layers to switch the magnetization of the free ferromagnetic layer. | 03-25-2010 |
| 20100247967 | MAGNETIC ELEMENT UTILIZING FREE LAYER ENGINEERING - A method and system for providing a magnetic element are described. The method and system include providing a pinned layer, a barrier layer, and a free layer. The free layer includes a first ferromagnetic layer, a second ferromagnetic layer, and an intermediate layer between the first ferromagnetic layer and the second ferromagnetic layer. The barrier layer resides between the pinned layer and the free layer and includes MgO. The first ferromagnetic layer resides between the barrier layer and the intermediate layer. The first ferromagnetic layer includes at least one of CoFeX and CoNiFeX, with X being selected from the group of B, P, Si, Nb, Zr, Hf, Ta, Ti, and being greater than zero atomic percent and not more than thirty atomic percent. The first ferromagnetic layer is ferromagnetically coupled with the second ferromagnetic layer. The intermediate layer is configured such that the first ferromagnetic layer has a first crystalline orientation and the second ferromagnetic layer has a second crystalline orientation different from the first ferromagnetic layer. | 09-30-2010 |
| 20110064969 | Magnetic Element Having Perpendicular Anisotropy With Enhanced Efficiency - Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy, a nonmagnetic spacer layer, and a free layer having a changeable free layer magnetization and perpendicular anisotropy. | 03-17-2011 |
Ga-Lane Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090120614 | HEAT COLLECTOR - A heat collector includes a heat absorption surface, an opposite heat focus surface and one or more surrounding sides. A matrix of the heat collector is a thermally conductive material. There is a plurality of adiabatic pores mixed within the matrix. A relative concentration distribution of the adiabatic pores increases from the heat absorption surface to the heat focus surface, and decreases from the surrounding sides to a center of the heat collector. The shape of the heat collector can be rectangular, cylindrical, prismatic, plate-shaped, square, or polyhedral. The heat collector can draw heat generated from electrical components, and collect the generated heat for reuse in order to enhance energy efficiency. | 05-14-2009 |
Geng Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100295078 | MANUFACTURE OF LIGHT EMITTING DEVICES WITH PHOSPHOR WAVELENGTH CONVERSION - A method of manufacturing a light emitting device comprises: a) depositing over substantially the entire surface of a LED diode wafer having an array of LEDs formed on a surface thereof a mixture of at least one phosphor material and a polymer material, wherein the polymer material is transmissive to light generated by the LEDs and to light generated by the at least one phosphor material; b) mechanically stamping the phosphor/polymer mixture with a stamp having features configured such as to form passages in the phosphor/polymer corresponding to electrode contact pads of each LED thereby enabling access to each electrode contact pad; c) curing the polymer; d) removing the stamp; and e) dividing the LED wafer into individual light emitting devices. The stamp comprises a dissolvable material (polyvinyl alcohol) and the stamp is removed by dissolving it using a solvent (e.g. water). | 11-25-2010 |
Gordon Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100013409 | LED Lamp - An LED lamp is provided in which the output light intensity of the LEDs in the LED lamp is adjusted based on the input voltage to the LED lamp. The LED lamp comprises one or more LEDs, and an LED driver configured to receive an input voltage and provide regulated current to said one or more LEDs, where the LED driver is configured to adjust the regulated current to said one or more LEDs according to the input voltage to adjust the output light intensity of said one or more LEDs. The LED lamp can be a direct replacement of conventional incandescent lamps in typical wiring configurations found in residential and commercial building lighting applications that use conventional dimmer switches that carry out dimming by changing the input voltage to the LED lamp. | 01-21-2010 |
| 20110012530 | ADAPTIVE DIMMER DETECTION AND CONTROL FOR LED LAMP - An LED lamp is provided in which the output light intensity of the LEDs in the LED lamp is adjusted based on the input voltage to the LED lamp. A dimmer control unit detects a type of dimmer switch during a configuration process. Using the detected dimmer type, the dimmer control unit generates control signals appropriate for the detected dimmer type to provide regulated current to the LEDs and to achieve the desired dimming effect. The LED lamp can be a direct replacement of conventional incandescent lamps in typical wiring configurations found in residential and commercial building lighting applications that use conventional dimmer switches. | 01-20-2011 |
Hong-Yi Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080222357 | Low power computer with main and auxiliary processors - A processing device comprises a processor, low power nonvolatile memory that communicates with the processor, high power nonvolatile memory that communicates with the processor. The processing device manages data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in the high power nonvolatile memory and a low power (LP) nonvolatile memory level for data in the low power nonvolatile memory. The LP nonvolatile memory level has a higher level in the cache hierarchy than the HP nonvolatile memory level. | 09-11-2008 |
| 20080222437 | Low power computer with main and auxiliary processors - An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode. | 09-11-2008 |
| 20080263324 | DYNAMIC CORE SWITCHING - A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode. | 10-23-2008 |
| 20080288748 | Dynamic core switching - A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled. | 11-20-2008 |
| 20100235660 | LOW POWER COMPUTER WITH MAIN AND AUXILIARY PROCESSORS - An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode. | 09-16-2010 |
| 20100329058 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line. | 12-30-2010 |
Hounien Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100177568 | READ MODE FOR FLASH MEMORY - A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed. | 07-15-2010 |
Hung Chuang Chen, Fremont, CA US
Irene Y. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080248589 | Sample Presentation Device - The present invention relates to sample presentation devices useful in performing analytical measurements. These devices have been configured to enable various aspects of liquid handling such as: retention, storage, transport, concentration, positioning, and transfer. Additionally, these devices can enhance the detection and characterization of analytes. The sample presentation devices of the present invention are comprised of one or more substrates having a plurality of zones of differing wettability. Methods of analyzing samples using the sample presentation device of the invention, as well as methods of making the sample presentation devices are disclosed. | 10-09-2008 |
| 20110070659 | SAMPLE PRESENTATION DEVICE - The present invention relates to sample presentation devices useful in performing analytical measurements. These devices have been configured to enable various aspects of liquid handling such as: retention, storage, transport, concentration, positioning, and transfer. Additionally, these devices can enhance the detection and characterization of analytes. The sample presentation devices of the present invention are comprised of one or more substrates having a plurality of zones of differing wettability. Methods of analyzing samples using the sample presentation device of the invention, as well as methods of making the sample presentation devices are disclosed. | 03-24-2011 |
James Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110069953 | DOCSIS PON - In accordance with a first aspect of the disclosure, a system is provided. The system includes: an optical line terminal (OLT) shelf including a plurality of optical line cards, each optical line card supporting at least one passive optical network (PON) interface for communicating with a corresponding set of optical network units (ONUs), the OLT shelf thereby corresponding to a plurality of sets the ONUs; a system card controller for controlling the plurality of optical line cards; and a DOCSIS proxy for emulating a cable modem (CM) SNMP agent for each ONU, the DOCSIS proxy being responsive to an SNP manager in a DOCSIS NMS to configure the ONUs accordingly. | 03-24-2011 |
| 20110072119 | Accelerated Cable Modem Restart Service - A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided. The system includes: a memory; and a caching entity configured to monitor transmissions from the provisioning server of the configuration files to the network nodes so as to both store the configurations files in the memory and to pass-through the configuration files to the network nodes; the caching entity being further configured to monitor requests to the provisioning server for respective ones of the DOCSIS configuration files from the network nodes, the caching entity being further configured to determine for each of the requests whether the requested configuration file has been previously requested node such that if the caching entity determines that the requested configuration file has been previously requested the caching entity retrieves the previously requested configuration file from the memory and returns the retrieved-from-memory configuration file to the network node. | 03-24-2011 |
Jawji Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100205504 | Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process - A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure. | 08-12-2010 |
| 20100208530 | Two Bits Per Cell Non-Volatile Memory Architecture - A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier. | 08-19-2010 |
Jia-Lih J. Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080208556 | Accurate pin-based memory power model using arc-based characterization - A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value. | 08-28-2008 |
Jinliang Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100300875 | MAGNETIC PARTICLE TRAPPER FOR A DISK SPUTTERING SYSTEM - A magnetic particle trapper for use in a sputtering system includes a roller cover plate having a plurality of openings arranged and dimensioned to accommodate a plurality of rollers associated with a mechanical transport mechanism of the sputtering system, and a plurality of magnets to trap magnetic particles, the plurality of magnets being attached to the roller cover plate in locations proximate to the plurality of openings. | 12-02-2010 |
Juinn-Yan Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080208488 | Device for Detecting Impact and Use Thereof - The present invention relates to a device for detecting an impact and use thereof. | 08-28-2008 |
Kim Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080250182 | SIP (SYSTEM IN PACKAGE) DESIGN SYSTEMS AND METHODS - SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system. | 10-09-2008 |
Ling-Chun Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080206756 | Biomarker panel for colorectal cancer - A panel of biomarkers has been identified for analysis of colorectal cancer. The panel, originally identified using a mouse colon cancer model, has been used to assess changes in human tissue from surgical and biopsy samples against a normal human control panel of biomarkers. The panel may be used for providing a cost effective, rapid, noninvasive procedure for risk assessment, early diagnosis, establishing prognosis, monitoring patient treatment, detecting relapse, and for the discovery of therapeutic intervention of colorectal cancer. | 08-28-2008 |
| 20090215169 | Method for regulating protein function in cells using synthetic small molecules - Methods and compositions for the rapid and reversible destabilizing of specific proteins using cell-permeable, synthetic molecules are described. Stability-affecting proteins, e.g., derived from FKBP and DHFR proteins are fused to a protein of interest and the presence or absence of the ligand is used to modulate the stability of the fusion protein. | 08-27-2009 |
Marcellus Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080290949 | APPARATUS AND METHOD FOR ASYMMETRIC CHARGE PUMP FOR AN AUDIO AMPLIFIER - An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD. | 11-27-2008 |
| 20090153107 | METHOD AND APPARATUS FOR REGULATING ELECTRICAL POWER FROM A NON-PERPETUAL POWER SOURCE - A method and system for regulating electrical power from a non-perpetual power source. In one implementation, the method includes receiving a variable power output from the non-perpetual power source, wherein a power amplitude of the variable power output substantially varies over time; and generating a regulated current output or a regulated voltage output based in part on the variable power output received from the non-perpetual power source. | 06-18-2009 |
Mingte Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090313642 | Adaptive Communication Application Programming Interface - A method and apparatus for inter-module communication is disclosed. The method includes defining a command definition, wherein the command definition comprises commands for interfacing with a multi-channel, multi-media, communication queuing system. The command definition can include, for example, driver object commands to request media type lists and command event lists, create drivers, request service, and release drivers. The command definition can also include, for example, service object commands to release service objects, notify when handling of an event is complete, invoke commands, release work items, suspend work items, resume work items, handle queued events, and cancel queued events. The command definition can also include, for example, client object commands to start a work item, release work items, save work item contexts, restore work item contexts, serialize work items, free work item storage, begin batch processing, and end batch processing. | 12-17-2009 |
Qinggen Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080209396 | Homepage for Modular Software - A multi-module application has a main module that generates a homepage user interface in a window for accessing a number of function modules of the application. Upon startup of the application, the main module parses a startup xml file that stores information about the function modules and generates the homepage user interface. When a user selects a function provided by a function module, the main module runs the function module and switches from the homepage user interface to a user interface of the function module in the same window. The user may return to the homepage from the function module by selecting a homepage button in the user interface of the function module. When a function module is added or removed from the application, an installer or uninstaller program updates the startup xml file by adding or removing information about the function module. | 08-28-2008 |
Sean Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090013216 | SYSTEM FOR FACILITATING PROBLEM RESOLUTION - Disclosed is a data processing system for facilitating problem resolution. The data processing system-implemented system includes a configuring module for configuring a system pathway that leads to a solution, and an associating module for associating a usage indicator with the symptom pathway, the usage indicator indicating a frequency in which the symptom pathway was previously implemented for successfully resolving previously experienced problems. | 01-08-2009 |
Shiaw-Min Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100311055 | COMPOSITIONS AND METHODS FOR TERMINATING A SEQUENCING REACTION AT A SPECIFIC LOCATION IN A TARGET DNA TEMPLATE - Compositions and methods for sequencing a template polynucleotide comprising a sequence of interest are provided herein. The compositions and methods employ at least one blocking probe that is designed to bind in a sequence-specific manner to a blocking sequence such that primer extension beyond the site where the blocking probe binds is reduced or prevented. | 12-09-2010 |
Shiping Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090081688 | Methods of detecting nucleic acids in individual cells and of identifying rare cells from large heterogeneous cell populations - Methods of detecting multiple nucleic acid targets in single cells through indirect capture of labels to the nucleic acids are provided. Methods of assaying the relative levels of nucleic acid targets through normalization to levels of reference nucleic acids are also provided. Methods of detecting individual cells, particularly rare cells from large heterogeneous cell populations, through detection of nucleic acids are described. Related compositions, systems, and kits are also provided. | 03-26-2009 |
Shuxian Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100123213 | METAL-INSULATOR-METAL CAPACITORS - Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field. | 05-20-2010 |
| 20100193904 | INTEGRATED CIRCUIT INDUCTOR WITH DOPED SUBSTRATE - An integrated circuit inductor and a substrate with doped regions are provided. The substrate may be a p-type substrate and the substrate may have n-type doped regions. The n-type doped regions may include n-type wells, deep n-type wells, and n+ regions. The n-type doped regions may be formed in a pattern of strips such as a triangular comb pattern of strips or a series of L-shaped strips. The strips may be oriented perpendicular to the spiral of the inductor. A positive bias voltage may be applied to the n-type doped regions to create a depleted region in the substrate between the n-type doped regions. The depleted region may increase the effective distance between the inductor and the substrate, minimizing undesired coupling effects between the inductor and the substrate and increasing the effectiveness of the inductor. | 08-05-2010 |
Stephanie Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090284733 | COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR SELECTING POLARIZATION SETTINGS FOR AN INSPECTION SYSTEM - Computer-implemented methods, carrier media, and systems for selecting polarization settings for an inspection system for inspection of a layer of a wafer are provided. One method includes detecting a population of defects on the layer of the wafer using results of each of two or more scans of the wafer performed with different combinations of polarization settings of the inspection system for illumination and collection of light scattered from the wafer. The method also includes identifying a subpopulation of the defects for each of the different combinations, each of which includes the defects that are common to at least two of the different combinations, and determining a characteristic of a measure of signal-to-noise for each of the subpopulations. The method further includes selecting the polarization settings for the illumination and the collection to be used for the inspection corresponding to the subpopulation having the best value for the characteristic. | 11-19-2009 |
| 20090299681 | METHODS AND SYSTEMS FOR GENERATING INFORMATION TO BE USED FOR SELECTING VALUES FOR ONE OR MORE PARAMETERS OF A DETECTION ALGORITHM - Methods and systems for generating information to be used for selecting values for parameter(s) of a detection algorithm are provided. One method includes without user intervention performing a scan of an area of a wafer using an inspection system and default values for parameter(s) of a detection algorithm to detect defects on the wafer. The method also includes selecting a portion of the defects from results of the scan based on a predetermined maximum number of total defects to be used for selecting values for the parameter(s) of the detection algorithm. The method further includes storing information, which includes values for the parameter(s) of the detection algorithm determined for the defects in the portion. The information can be used to select the values for the parameter(s) of the detection algorithm to be used for the inspection recipe without performing an additional scan of the wafer subsequent to the scan. | 12-03-2009 |
Steve Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090067551 | GENERATING AND COMMUNICATING SOURCE IDENTIFICATION INFORMATION TO ENABLE RELIABLE COMMUNICATIONS - A method of generating Source Identification information from a source packet stream and reliably transmitting the Source Identification information from a source to a destination over a communications channel is provided. The method operates on a set of source packets, wherein Source Identification information for each source packet to be transmitted is derived and delivered with the Source Identification information of all or most other source packets of an associated source block. The method includes techniques to minimize the network bandwidth required to deliver Source Identification information and techniques to overcome network impairments. When combined with FEC techniques, retransmission techniques, or combinations of FEC techniques and retransmission techniques, the methods described herein allow receivers to recover lost source packets, while simultaneously ensuring that the original source packets are not modified and thereby ensuring backwards compatibility for legacy receivers. | 03-12-2009 |
Xiangrong Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090222388 | Method of and system for hierarchical human/crowd behavior detection - The present invention is directed to a computer automated method of selectively identifying a user specified behavior of a crowd. The method comprises receiving video data but can also include audio data and sensor data. The video data contains images a crowd. The video data is processed to extract hierarchical human and crowd features. The detected crowd features are processed to detect a selectable crowd behavior. The selected crowd behavior detected is specified by a configurable behavior rule. Human detection is provided by a hybrid human detector algorithm which can include Adaboost or convolutional neural network. Crowd features are detected using textual analysis techniques. The configurable crowd behavior for detection can be defined by crowd behavioral language. | 09-03-2009 |
Xiaoheng "cora" Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090219827 | REGISTERED STATE CHANGE NOTIFICATION FOR A FIBRE CHANNEL NETWORK - Disclosed herein are various aspects of a Fibre Channel (Fibre Channel) fabric having switches that employ Registered State Change Notifications (RSCNs) with enhanced payloads. Two types of RSCN message formats are provided, both including status information about the affected device(s). In one embodiment, a RSCN message format for inter-switch communication provides various information about the affected devices according to one of a plurality of predetermined formats. In another embodiment, a node device RSCN message format provides information about a port state, the identification of the affected port, along with the port and node world wide names and the FC-4 types supported by the node. | 09-03-2009 |
Xiaoxin Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090100250 | SWITCHING BETWEEN MULTIPLE SOFTWARE ENTITIES USING DIFFERENT OPERATING MODES OF A PROCESSOR - The computer program includes a virtualization software that is executable on the new processor in the legacy mode. The new processor includes a legacy instruction set for a legacy operating mode and a new instruction set for a new operation mode. The switching includes switching from the new instruction set to the legacy instruction set and switching paging tables. Each of the new operating mode and the legacy operating mode has separate paging tables. The switch routine is incorporated in a switch page that is locked in physical memory. The switch page has a first section to store a part of switching instructions conforming to the new instruction set and a second section to store another part of the switching instructions conforming to the legacy instruction set. | 04-16-2009 |
| 20090106524 | METHODS FOR ACCESSING MULTIPLE PAGE TABLES IN A COMPUTER SYSTEM - A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access. | 04-23-2009 |
Yajuan Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080303780 | DRIVING METHODS AND CIRCUIT FOR BI-STABLE DISPLAYS - The disclosure is directed toward driving methods and a driving circuit which are particularly suitable for bi-stable displays. In certain embodiments, methods provide the fastest and most pleasing appearance to the desired image while maintaining the optimal image quality over the life expectancy of an electrophoretic display device. | 12-11-2008 |
| 20090096745 | APPROACH TO ADJUST DRIVING WAVEFORMS FOR A DISPLAY DEVICE - The present invention is directed to methods for adjusting or selecting driving waveforms in order to achieve a consistent optical performance of a display device. When a method of the present invention is applied, even if there are changes in the display medium due to temperature variation, photo-exposure or aging, the optical performance can be maintained at a desired level. | 04-16-2009 |
| 20090267970 | DRIVING METHODS FOR BISTABLE DISPLAYS - The disclosure relates to driving methods for bistable displays, in particular, driving methods comprising interleaving driving waveforms. | 10-29-2009 |
| 20100301280 | METHODS AND COMPOSITIONS FOR IMPROVED ELECTROPHORETIC DISPLAY PERFORMANCE - The invention is directed to novel methods and compositions useful for improving the performance of electrophoretic displays. The methods comprise adding a high absorbance dye or pigment, or conductive particles, or a conductive filler in the form of nanoparticles and having a volume resistivity of less than about 10 | 12-02-2010 |
| 20110157682 | DISPLAY CELL STRUCTURE AND ELECTRODE PROTECTING LAYER COMPOSITIONS - The invention is directed to compositions of display cell structure and electrode protecting layers for improving the performance of display devices. The composition comprises a polar oligomeric or polymeric material having a glass transition temperature below about 100° C., and the resulting display cells or electrode protecting layer have an average crosslinking density of below about 1 crosslink point per 80 Dalton molecular weight. | 06-30-2011 |
Yencheng Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100260201 | METHOD AND SYSTEM FOR AN EXTENDED RANGE ETHERNET LINE CODE - Aspects of a method and system for an extended range Ethernet line code are provided. One or more ternary encoded bitstreams may be generated and transmitted. The generating may comprise mapping 3-bit binary IDLE patterns having a least significant bit of zero to a non-zero ternary value, and mapping 3-bit binary IDLE patterns having a non-zero least significant bit to a ternary zero. The generating may comprise receiving binary data via a media independent interface, mapping each 4-bit portion of said received binary data to a ternary symbol comprising two ternary bits, and transmitting said ternary symbol over said one or more physical channels. Data portions of the one or more ternary encoded bitstreams may be generated by mapping 3-bit binary patterns to 2-bit ternary symbols. One of the nine possible 2-bit ternary symbols may be reserved for control portions of said one or more ternary encoded bitstreams. | 10-14-2010 |
Yingjian Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110134567 | PERPENDICULAR MAGNETIC WRITE HEAD WITH WRAP-AROUND SHIELD, SLANTED POLE AND SLANTED POLE BUMP FABRICATED BY DAMASCENE PROCESS - A magnetic write head having a write pole with a tapered trailing edge. The write head has a non-magnetic step layer and a non-magnetic bump formed on the front edge of the magnetic step layer. A non-magnetic trailing gap layer is formed over the tapered trailing edge of the write pole and over the non-magnetic bump and over the non-magnetic step layer. A magnetic trailing shield is formed over at least a portion of the non-magnetic gap layer. | 06-09-2011 |
| 20110134568 | PMR WRITER AND METHOD OF FABRICATION - Methods for fabrication of tapered magnetic poles with a non-magnetic front bump layer. A magnetic pole may have a tapered surface at or near an air bearing surface (ABS), wherein a thickness of the write pole increases in a direction away from the ABS. A non-magnetic front bump layer may be formed on the tapered surface of the magnetic pole and away from the ABS. The front bump layer may increase the separation distance between a shield layer and the magnetic pole near the tapered surface, thereby improving the performance of the write head. | 06-09-2011 |
| 20110146062 | METHOD FOR MANUFACTURING A MAGNETIC WRITE HEAD HAVING A WRAP AROUND SHIELD THAT IS MAGNETICALLY COUPLED WITH A LEADING MAGNETIC SHIELD - A method for manufacturing a magnetic write head having a leading magnetic shield and a trailing magnetic shield that are arranged to prevent the lost of magnetic write field to the trailing magnetic shield. The write head includes a non-magnetic step layer that provides additional spacing between the trailing magnetic shield and the write pole at a region removed from the air bearing surface. | 06-23-2011 |
| 20110151279 | MAGNETIC WRITE HEAD MANUFACTURED BY AN ENHANCED DAMASCENE PROCESS PRODUCING A TAPERED WRITE POLE WITH A NON-MAGNETIC SPACER AND NON-MAGNETIC BUMP - A magnetic write head having a tapered trailing edge and having a magnetic layer formed over a trailing edge of the write pole at a location recessed from the ABS, the magnetic layer being separated from the trailing edge of the write pole by a thin non-magnetic layer. The thin non-magnetic layer is preferably sufficiently thin that the magnetic layer can function as a portion of the write pole in a region removed from the ABS. A trailing magnetic shield is formed over the write pole and is separated from the write pole by a non-magnetic trailing gap layer. A non-magnetic spacer layer can be formed over the magnetic layer to provide additional separation between the magnetic layer and the trailing magnetic shield. | 06-23-2011 |
Yuhui Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090322234 | LED DRIVER WITH MULTIPLE FEEDBACK LOOPS - An LED driver includes at least two interlocked closed feedback loops. One feedback loop controls the duty cycle of the on/off times of a switch connected in series to the LED string, and the other feedback loop controls the duty cycle of the on/off times of a power switch in the switching power converter that provides a DC voltage applied to the LED string. The LED driver of the present invention achieves fast control of the LED brightness and current sharing among multiple LED strings simultaneously in a power-efficient and cost-efficient manner. | 12-31-2009 |
| 20110101937 | Voltage Regulator with Virtual Remote Sensing - An automatic voltage compensation circuit in a voltage regulator compensates the output voltage for a voltage drop along lines leading to a remote load. A load capacitor is connected across the load for providing a low impedance across the load during a test phase of the regulator. In one embodiment, during the test phase, the load current is changed up or down a small percentage (e.g., 10%). As a result, the regulator voltage changes due only to the line resistance since the load is bypassed by the load capacitor. The voltage drop at full load current is then derived by detecting the change in regulator output voltage (a fractional voltage drop) and multiplying it. The normal mode is resumed, and the derived voltage drop is added to the regulator output by either compensating the feedback loop or by adding the voltage drop to the output of the regulator. | 05-05-2011 |
Yu-Jiuan Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100032580 | Compact Accelerator For Medical Therapy - A compact accelerator system having an integrated particle generator-linear accelerator with a compact, small-scale construction capable of producing an energetic (˜70-250 MeV) proton beam or other nuclei and transporting the beam direction to a medical therapy patient without the need for bending magnets or other hardware often required for remote beam transport. The integrated particle generator-accelerator is actuable as a unitary body on a support structure to enable scanning of a particle beam by direction actuation of the particle generator-accelerator. | 02-11-2010 |
| 20100060207 | COMPACT ACCELERATOR FOR MEDICAL THERAPY - A compact accelerator system having an integrated particle generator-linear accelerator with a compact, small-scale construction capable of producing an energetic (˜70-250 MeV) proton beam or other nuclei and transporting the beam direction to a medical therapy patient without the need for bending magnets or other hardware often required for remote beam transport. The integrated particle generator-accelerator is actuable as a unitary body on a support structure to enable scanning of a particle beam by direction actuation of the particle generator-accelerator. | 03-11-2010 |
| 20110101891 | VIRTUAL GAP DIELECTRIC WALL ACCELERATOR - A virtual, moving accelerating gap is formed along an insulating tube in a dielectric wall accelerator (DWA) by locally controlling the conductivity of the tube. Localized voltage concentration is thus achieved by sequential activation of a variable resistive tube or stalk down the axis of an inductive voltage adder, producing a “virtual” traveling wave along the tube. The tube conductivity can be controlled at a desired location, which can be moved at a desired rate, by light illumination, or by photoconductive switches, or by other means. As a result, an impressed voltage along the tube appears predominantly over a local region, the virtual gap. By making the length of the tube large in comparison to the virtual gap length, the effective gain of the accelerator can be made very large. | 05-05-2011 |
Zheng Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100003246 | Novel heterocyclic compounds and uses therof - New substituted heterocyclic compounds, compositions containing them, and methods of using them for the inhibition of Raf kinase activity are provided. The new compounds and compositions may be used either alone or in combination with at least one additional agent for the treatment of a Raf kinase mediated disorder, such as cancer. | 01-07-2010 |
Zhiqiang Chen, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110176144 | Polarization Based Delay Line Interferometer - This invention provides a compact delay-line interferometer that can be used in Differential Phase Shift Keying (DPSK) and Differential Quardratic Phase Shift Keying (DQPSK) demodulators. The delay-line interferometer is based on polarization components including beam shifter, beam splitter and wave plates. The realized demodulators can be used as either discrete components or integrated with balanced detectors. Time delay generated in the interferometer can be controlled with a phase shifter, using either thermal, piezoelectric, mechanical of electrical means. This application claims priority to US Provisional Patent Application Ser. No. 61/238,687, filed Sep. 1, 2009, titled “Polarization Based Interferometer.” This application also claims priority to US Provisional Patent Application Ser. No. 61/295,766, filed Jan. 18, 2010, titled “Delay-Line-Interferometer for Integration with Balanced Receivers.” | 07-21-2011 |
| 20110176200 | Delay-Line-Interferometer for Integration with Balanced Receivers - This invention provides a DPSK demodulator and a DQPSK demodulator. Both of the demodulators are based on polarization delay-line interferometers. They can be integrated with photodetectors in fiber-optic communication systems. The demodulators consist of polarization beam shifter, polarization beam splitter and wave plates. Coupling of the demodulators with photodetectors can be through free space or fibers. Time delay generated in the interferometer can be controlled with a phase shifter, using either thermal, piezoelectric, mechanical or electrical means. Examples of phase shifter using a piezo bender and an actuator respectively are also disclosed. | 07-21-2011 |