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| 20100228928 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 09-09-2010 |
| 20100228940 | MEMORY BLOCK MANAGEMENT - Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective. | 09-09-2010 |
| 20120124304 | MEMORY BLOCK MANAGEMENT - One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block. | 05-17-2012 |
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| 20090004807 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 01-01-2009 |
| 20090108328 | Array Of Non-volatile Memory Cells - An array of nonvolatile memory cells comprises a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar surface. A plurality of non-volatile memory cell units are arranged in a plurality of rows and columns in the substrate. Each cell unit comprises a first region of a second conductivity type in the substrate along the planar surface. A second region of the second conductivity type is in the substrate along the planar surface, spaced apart from the first region. A channel region is between the first region and the second region. The channel region is characterized by three portions: a first portion, a second portion and a third portion, with the second portion between the first portion and the third portion, and the first portion adjacent to the first region, and the third portion adjacent to the second region. A first floating gate is over the first portion of the channel region, and is insulated therefrom. A first control gate is over the first floating gate and is capacitively coupled thereto. A first erase gate is over the first region and is insulated therefrom. A word line is over the second portion and is insulated therefrom. A second erase gate is over the second region and is insulated therefrom. A second floating gate is over the third portion and is insulated therefrom. A second control gate is over the second floating gate and is capacitively coupled thereto. Cell units in the same row share the word line in common. Cell units in the same column share the first region in common to one side, the first erase gate in common, the second region in common to the other side and the second erase gate in common, and the first and second control gates in common. Cell units in the same column share the first control gate in common and the second control gate in common. Electrical contacts are made to the array only along extremities of the array at first and second regions. | 04-30-2009 |
| 20090256590 | STORAGE ELEMENT FOR CONTROLLING A LOGIC CIRCUIT, AND A LOGIC DEVICE HAVING AN ARRAY OF SUCH STORAGE ELEMENTS - The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output. | 10-15-2009 |
| 20090309182 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - A first embodiment of an Electrostatic Discharge (ESD) structure for an integrated circuit for protecting the integrated circuit from an ESD signal, has a substrate of a first conductivity type. The substrate has a top surface. A first region of a second conductivity type is near the top surface and receives the ESD signal. A second region of the second conductivity type is in the substrate, separated and spaced apart from the first region in a substantially vertical direction. A third region of the first conductivity type, heavier in concentration than the substrate, is immediately adjacent to and in contact with the second region, substantially beneath the second region. In a second embodiment, a well of a second conductivity type is provided in the substrate of the first conductivity type. The well has a top surface. A first region of the second conductivity type is near the top surface. A second region of the second conductivity type is in the well, substantially along the bottom of the well. A third region of the first conductivity type, is immediately adjacent to and in contact with the second region, substantially beneath the second region. A fourth region of the first conductivity type is in the well, along the top surface thereof, and spaced apart from the first region. The first region and the fourth region receive the ESD signal. | 12-17-2009 |
| 20100173468 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 07-08-2010 |
| 20100259979 | Self Limiting Method For Programming A Non-volatile Memory Cell To One Of A Plurality Of MLC Levels - A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state. | 10-14-2010 |
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| 20090176454 | Methods and apparatus for wireless device coexistence - Methods and apparatus for compensating for the effects of interference between multiple wireless communication apparatus. In one embodiment, the method comprises providing a first wireless communication apparatus operating in a first band and a second wireless communication apparatus operating at least partly in the first band, where the second wireless communication apparatus operates according to a different communication protocol than the first wireless communication apparatus. Interference is compensated for between the first wireless communication apparatus and the second wireless communication apparatus by selecting and operating according to one of a plurality of operational protocols. In another embodiment, the first wireless communication apparatus and the second wireless communication apparatus operate in a closed-loop relationship to cooperatively compensate for communication interference. | 07-09-2009 |
| 20090257379 | Methods and apparatus for network capacity enhancement for wireless device coexistence - Methods and apparatus for enhancing network capacity in a network comprising multiple wireless communication that overlap at least partly in frequency spectrum. In one embodiment, the apparatus comprises a portable device such as a laptop or smartphone having both a WLAN (e.g., Wi-Fi) interface and a PAN (e.g., Bluetooth) interface which each operate with approximately the same frequency range. One variant places the WLAN interface into a power-saving mode as a default, thereby mitigating interference with the PAN interface in cases where the WLAN interface is not in active use. In another variant, an aggressive PAN management algorithm is used to enforce network policy on the PAN interface, thereby mitigating interference between the PAN interface and the WLAN interfaces of other devices in the network (as well as the parent device). AP-based variants are also described. Methods of operation and doing business utilizing the aforementioned apparatus are also disclosed. | 10-15-2009 |
| 20090323652 | Methods and apparatus for antenna isolation-dependent coexistence in wireless systems - Methods and apparatus for selectively switching one or more antennas in a multiple-input, multiple-output (MIMO) antenna array so as to mitigate interference with another RF interface within the same space-constrained device, based on radio frequency isolation. In one embodiment, the MIMO interface comprises a WLAN interface having a 2×2 or 3×3 array of antennae which are placed in a wireless device in an asymmetric fashion with respect to the antenna of the second interface, and the other interface comprises a PAN (e.g., Bluetooth) interface operating in an overlapping frequency band (e.g., ISM band). When both interfaces are operating, interference is mitigated through selectively switching off one or more of the MIMO antennae, and using the remaining antenna(e) having the best isolation from the Bluetooth antennae. This approach allows simultaneous operation of both interferences without significant degradation to user experience or the operation of either interface, and may also provide power savings critical to mobile device battery longevity. | 12-31-2009 |
| 20100240317 | METHODS AND APPARATUS FOR TESTING AND INTEGRATION OF MODULES WITHIN AN ELECTRONIC DEVICE - Methods and apparatus for analysis of electronic components such as radio transceivers (for example, WLAN, Bluetooth, cellular, GPS). In one embodiment, a “black box” is diagnosed in its final device application and layout, using a series of software test routines or suites. The test suites provide simultaneous monitoring of multiple non-overlapping status indicators. Each test suite can be selectively enabled or disabled, and may also provide runtime modification of one or more parameters, and or intelligent testing of system operation. In another embodiment, multiple black box modules within a single form factor device are simultaneously run; the interference levels between the black box modules (as well as other parameters) are independently measured, displayed and logged to the user. Exemplary embodiments are described in reference to a Bluetooth module and WLAN module operating within a spatially restricted device (such as a desktop/laptop computer, “smartphone”, Bluetooth mouse and keyboard). | 09-23-2010 |
| 20110081858 | METHODS AND APPARATUS FOR ENHANCED COEXISTENCE ALGORITHMS IN WIRELESS SYSTEMS - Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described. | 04-07-2011 |
| 20110090982 | METHODS AND APPARATUS FOR DYNAMIC WIRELESS DEVICE COEXISTENCE - Methods and apparatus for dynamically compensating for the effects of interference between multiple wireless communications apparatus. In one embodiment, the method comprises providing a first wireless communication apparatus operating in a first band and a second wireless communication apparatus operating in the same first band (or proximate to the first band and with a comparatively high transmitter power), where the second wireless communication apparatus operates according to a different communication protocol than the first wireless communication apparatus and further change in physical configuration with respect to one another. Based on the physical configuration, interference is compensated for between the first wireless communication apparatus and the second wireless communication apparatus “on the fly” by selecting and operating according to one of a plurality of operational protocols. | 04-21-2011 |
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| 20100246584 | MAINTAINING PACKET ORDER USING HASH-BASED LINKED-LIST QUEUES - Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue. | 09-30-2010 |
| 20100284271 | PACKET SPRAYING FOR LOAD BALANCING ACROSS MULTIPLE PACKET PROCESSORS - A network device includes multiple packet processing engines implemented in parallel with one another. A spraying component distributes incoming packets to the packet processing engines using a spraying technique that load balances the packet processing engines. In particular, the spraying component distributes the incoming packets based on queue lengths associated with the packet processing engines and based on a random component. In one implementation, the random component is a random selection from all the candidate processing engines. In another implementation, the random component is a weighted random selection in which the weights are inversely proportional to the queue lengths. | 11-11-2010 |
| 20120027019 | MAINTAINING PACKET ORDER USING HASH-BASED LINKED-LIST QUEUES - Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue. | 02-02-2012 |
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| 20090257459 | SYSTEM, APPARATUS, AND METHOD FOR INCREASING RESILIENCY IN COMMUNICATIONS - A transmitting system inserts runt abort packets in an outgoing data stream during idle time inter-frame time fill. The runt abort packets cause the receiving system to synchronize itself to the transmitting system so that even if an error during inter-frame time fill causes the receiving system to go into an erroneous state, the receiving system will be synchronized with the transmitting system before receiving valid data. In one embodiment, the transmitting system transmits data in packets over SONET, The packet data is scrambled at the transmitting end and descrambled at the receiving end. Runt abort packets. sent during inter-frame time fill resynchronize the descrambler. If there is an error in the inter-frame time fill bytes, causing the receiving end descrambler to no longer be synchronized with the transmitting end scrambler, the runt abort packets will cause the descrambler to resynchronize state with the transmitting scrambler. | 10-15-2009 |
| 20100177638 | HIGH PERFORMANCE PROBABILISTIC RATE POLICER - A data flow rate policer enforces data flow policies for a number of data flows using a probabilistic policy enforcement mechanism. The policer includes a memory that stores the state of each data flow in a compact data structure. Additionally, the policer includes one or more policing engines that implement the actual data flow policies based on information derived from the data structures. The policing engines may be implemented in hardware to increase performance. | 07-15-2010 |
| 20110010474 | LOW LATENCY REQUEST DISPATCHER - A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue. | 01-13-2011 |
| 20110208926 | LOW LATENCY REQUEST DISPATCHER - A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue. | 08-25-2011 |
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| 20080263750 | Headwear with signal generating capability - A headwear with signal generating capability includes: a headwear body; a signal output unit mounted on the headwear body for generating at least one of audio and video signals; a control circuit including a controller coupled electrically to the signal output unit for controlling activation and deactivation of the signal output unit; and a switch mounted on the headwear body and coupled electrically to the control circuit for controlling operating states of the control circuit. | 10-30-2008 |
| 20090183401 | MESSAGE CARD - A message card includes: a card body having first and second leaves, the card body being foldable and unfoldable in a manner that the first leaf is movable toward and away from the second leaf between closed and opened positions; a mounting base provided on the second leaf; a supporting mechanism mounted on the mounting base and defining two opposite end openings that are spaced apart from each other by a gap; a circuit unit; a switch mounted on the mounting base, coupled electrically to the circuit unit, and having an actuating member extending into the gap; and a flexible driving lever attached to the first leaf, extending through the end openings, and co-movable with the first leaf relative to the second leaf. The driving lever has a driving segment that is received in the gap to drive movement of the actuating member of the switch. | 07-23-2009 |
| 20090220928 | ARTICLE WITH CIRCUIT ACTUATING CAPABILITY - An article with circuit actuating capability includes a first article part, a second article part formed with a pocket and linked to the first article part such that the first and second article parts being movable relative to each other, the pocket having an access opening, and a circuit built in the pocket in the second article part and accessible through the access opening of the pocket for controlling circuit states of the circuit. | 09-03-2009 |
| 20100038276 | Zipper assembly with a circuit actuating capability and bag having the zipper assembly - A zipper assembly includes: first and second zipper tapes; a zipper chain having one end and including first teeth secured to the first zipper tape and second teeth secured to the second zipper tape; a zipper slider mounted slidably on the zipper chain for engaging and disengaging the first and second teeth; an end stopper secured to the first and second zipper tapes, and disposed adjacent to the end of the zipper chain; and a switch mounted to the end stopper in such a manner that the switch is switched on by the zipper slider so as to actuate a circuit when the zipper slider is moved to the end of the zipper chain. | 02-18-2010 |
| 20100089786 | GIFT PACKAGE HAVING CIRCUIT ACTUATING CAPABILITY - A gift package includes: a box body having a partitioning plate dividing an inner space in the box body into first and second chambers and adapted to abut against an article, the box body being provided with a lid for covering and uncovering an access opening of the box body; a signal output unit mounted in the second chamber; a circuit board mounted securely in the second chamber and provided with a controller that is electrically coupled to the signal output unit for controlling activation and deactivation of the signal output unit; and a switch operable through a selected one of the lid and the article to activate the signal output unit. | 04-15-2010 |
| 20100264045 | CUP ASSEMBLY WITH CIRCUIT ACTUATING CAPABILITY - A cup assembly with circuit actuating capability comprises: a cup body having a bottom recess that is defined by a recess-defining wall and that has an open end, the recess-defining wall being provided with a threaded structure; a module support having a base part that covers the open end of the bottom recess, and a threaded confining part that is connected to the base part, that is received in the bottom recess, that defines an accommodating space, and that engages threadedly with the threaded structure; and a signal producing module mounted on the base part, received in the accommodating space, and including a signal producing member and a first switch that is coupled to the signal producing member and that is operable to enable and disable the signal producing member. | 10-21-2010 |
| 20110273280 | MEDICAMENT REMINDER DEVICE - A medicament reminder device for reminding patients to ingest or administer medicaments includes an output ( | 11-10-2011 |
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| 20100153912 | Variable type knowledge based call specialization - Variable type knowledge based call specialization is disclosed. An indication is received that a variable that is an argument of a function or operation the behavior of which depends at least in part on a data type of the argument is of a first data type. Machine code that implements a first behavior that corresponds to the first data type, but not a second behavior that corresponds to a second data type other than the first data type, is generated for the function or operation. | 06-17-2010 |
| 20100153929 | Converting javascript into a device-independent representation - A device-independent intermediate representation of a source code is generated and stored, e.g., in a memory or other storage mechanism. The stored intermediate representation of the source code is used to generate a device-specific machine code corresponding to the source code. The stored intermediate representation may be updated, e.g., periodically, for example by obtaining an updated version of the source code and compiling the updated source code to generate an updated intermediate representation. The stored intermediate representation may be based on source code received from a device that is synchronized with which a compiling device that generates the device-specific machine code. In some cases, the stored intermediate representation may be used to generate for each of a plurality of devices a corresponding device-specific machine code. | 06-17-2010 |
| 20120030653 | ASSUMPTION-BASED COMPILATION - Techniques for processing source code written in a traditionally interpreted language such as JavaScript, or another dynamic and/or interpreted language, are disclosed. In one example, compiled code associated with the source code is constructed and executed. An assumption on which a specific aspect of the compiled code is based (e.g., an optimization) is tested at a checkpoint of the compiled code. A roll over to fallback code is performed if the test indicates the assumption is not true. | 02-02-2012 |
| 20120030659 | CONSTRUCTING RUNTIME STATE FOR INLINED CODE - Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at which execution is to begin is constructed. In some examples, execution of the portion of code is initiated. In some examples, a program counter associated with the portion of the code is used to initiate execution of the code. In some examples, the computer code comprises a fallback code associated with a previously executing code. | 02-02-2012 |
| 20120030661 | OBSERVATION AND ANALYSIS BASED CODE OPTIMIZATION - Observation and analysis based optimization of software code is disclosed. An expected value is chosen for a dynamic attribute that cannot be determined, prior to execution of the associated software code, to be guaranteed to have that expected value at runtime. An optimized version of the software code is generated, including one or more optimizations based on an assumption that the dynamic attribute will have the expected value. Non-exhaustive examples of a dynamic attribute include a variable type; a location in memory; a location in which a global object, property, or variable is stored; the contents of a global function or method; and a value of a global property or variable. A check is performed during execution of the optimized version of the software code, prior to executing the portion that has been optimized based on the assumption, to verify that the dynamic attribute has the expected value. In the event that it is determined at runtime that the dynamic attribute does not have the expected value, execution reverts to backup code that is not based on the assumption that dynamic attribute will have the expected value. | 02-02-2012 |
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| 20080252335 | ROBUST AND ECONOMIC SOLUTION FOR FPGA BITFILE UPGRADE - A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result: the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA. | 10-16-2008 |
| 20080310440 | Network interface system with filtering function - A network interface system with packet filtering function is disclosed herein. The network interface system includes interfaces, a packet buffer and a controller. The packet buffer stores data packets received by the network interface system. The controller provides security defense for the host system and the network by filtering the data packets stored in the packet buffer. The controller controls the packet buffer abandoning a data packet if the data packet is identified as an unsafe packet. The controller also includes a regulator for controlling a transferring order of the data packets. Thus, the network interface system can drop unsafe data packet and transfer data packets considered as safe information. The data packets can be processed in a sequence according to preset priority rules. | 12-18-2008 |
| 20100138909 | VPN AND FIREWALL INTEGRATED SYSTEM - The present disclosure provides an integrated VPN/Firewall system that uses both hardware (firmware) and software to optimize the efficiency of both VPN and firewall functions. The hardware portions of the VPN and firewall are designed in flexible and scalable layers to permit high-speed processing without sacrificing system security. The software portions are configured to provide interfacing with hardware components, report and rules management control. | 06-03-2010 |
| 20100211544 | SYSTEM WITH SESSION SYNCHRONIZATION - A computer-readable medium having computer-executable modules is disclosed. The computer-executable modules include a first session database for storing multiple sessions indicating information interchange between at least two communicating devices. The computer-executable modules further include a controller operable for selecting a session from the first session database according to a session update rate indicating the number of sessions updated in the first session database during a given period of time and for synchronizing the session from the first session database to a second session database. | 08-19-2010 |
| 20110075678 | NETWORK INTERFACE SYSTEM WITH FILTERING FUNCTION - A network interface system for transferring a data packet between a host system and a network includes multiple matchers and multiple queues. The matchers match the data packet with multiple rules from the host system to generate multiple matching results and allocate a transferring priority to the data packet according to the rules. The queues correspond to the matchers respectively. A queue of the queues stores information indicating the transferring priority for the data packet according to the matching results and priorities of matchers. | 03-31-2011 |
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| 20090128389 | Multi-bit Per Stage Pipelined Analog to Digital Converters - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches. | 05-21-2009 |
| 20090128391 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period. | 05-21-2009 |
| 20090219057 | Systems and methods for determining an out of band signal - Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock. | 09-03-2009 |
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| 20100130013 | SLURRY COMPOSITION FOR GST PHASE CHANGE MEMORY MATERIALS POLISHING - A CMP method for polishing a phase change alloy on a substrate surface including positioning the substrate comprising a phase change alloy material on a platen containing a polishing pad and delivering a polishing slurry to the polishing pad. The polishing slurry includes colloidal particles with a particle size less than 60 nm, in an amount between 0.2% to about 10% by weight of slurry, a pH adjustor, a chelating agent, an oxidizing agent in an amount less than 1% by weight of slurry, and polyacrylic acid. The substrate on the platen is polished to remove a portion of the phase change alloy. A rinsing solution for rinsing the substrate on the platen includes deionized water and at least one component in the deionized water where the component selected from the group consisting of polyethylene imine, polyethylene glycol, polyacrylic amide, alcohol ethoxylates, polyacrylic acid, an azole containing compound, benzo-triazole, and combinations thereof. | 05-27-2010 |
| 20110265816 | DISK-BRUSH CLEANER MODULE WITH FLUID JET - Embodiments of the present invention relates to an apparatus and method for cleaning a substrate using a disk brush. One embodiment provides a substrate cleaner comprising a substrate chuck disposed in the processing volume, and a brush assembly disposed in the processing volume, wherein the brush assembly comprises a disk brush movably disposed opposing the substrate chuck, and a processing surface of the disk brush contacts a surface of the substrate on the substrate chuck. | 11-03-2011 |
