Patent application number | Description | Published |
20140015561 | HIGH FREQUENCY PROBE CARD - A high frequency probe card includes at least one substrate having at least one first opening, an interposing plate disposed on the at least one substrate and having at least one second opening corresponding to the at least one first opening, a circuit board disposed on the interposing plate and having a third opening corresponding to the at least one first and second openings, and at least one probe module including at least one N-type ground probe and at least one high frequency signal probe passing through the corresponding substrate, the interposing plate and the third opening and being electrically connected with the circuit board. Each high frequency signal probe includes an N-type signal probe and a first conductor corresponding to the N-type signal probe and being electrically connected with the N-type ground probe. An insulation layer is disposed between the first conductor and the N-type signal probe. | 01-16-2014 |
20140016123 | PROBE HOLDING STRUCTURE AND OPTICAL INSPECTION DEVICE EQUIPPED WITH THE SAME - A probe holding structure includes a substrate and a plurality of holding modules. The substrate has an opening and a plurality of grooves arranged around a periphery of the opening. The holding modules are connected with the grooves, respectively. Each holding modules includes a fixing member and a plurality of probes. The fixing member is connected with a corresponding groove. The probes are connected with the fixing member and pass through the corresponding groove. The probe holding structure is combined with a lens adjusting mechanism having a lens to form an optical inspection device for testing electric characteristics of chips. | 01-16-2014 |
20140016124 | OPTICAL INSPECTION DEVICE - An optical inspection device includes a circuit board having at least one first opening, a mounting plate disposed on a top or bottom surface of the circuit board and having at least one second opening corresponding to the at least one first opening respectively, at least one lens holder received in the at least one second opening, and at least one probe module disposed on a bottom surface of the mounting plate or the bottom surface of the circuit board, corresponding to the at least one lens holder respectively, and having probes electrically connected with the circuit board. Each lens holder has an accommodation for accommodating a lens, and is operatable to do a position adjusting motion in the corresponding second opening. | 01-16-2014 |
Patent application number | Description | Published |
20140352460 | Probe Needle and Probe Module Using the Same - A probe needle includes a head, a tail and a body connected between the head and the tail and provided with a first flat section curvedly extending from the head towards the tail for providing sufficient deformation when the tail is pressed on a device under test, and a second flat section neighbored to the first flat section for supporting the probe needle in between upper and lower dies. When the probe needles are used in a probe module, the probe needles can be arranged with a pitch same as that of the conventional probe needles even though the probe needles are formed from posts having a relatively greater diameter than that of the posts for making the conventional probe needles, such that the probe needles may have enhanced current withstanding capacity and prolonged lifespan. | 12-04-2014 |
20150033553 | ASSEMBLY METHOD OF DIRECT-DOCKING PROBING DEVICE - An assembly method of direct-docking probing device is provided. First, a space transforming plate made by back-end-of-line semiconductor manufacturing process is provided, so the thickness of the space transforming plate is predetermined by the client of probe card manufacturer. Then a reinforcing plate in which a plurality of circuits disposed is provided, which has larger mechanical strength than the space transforming plate. After that the reinforcing plate and the space transforming plate are joined and electrically connected by a plurality of solders so as to form a space transformer. Then, a conductive elastic member and a probe interface board are provided. Thereafter, the space transformer and the conductive elastic member are mounted on the probe interface board. After that, at least one vertical probe assembly having a plurality of vertical probes is mounted on the space transforming plate, and the vertical probes is electrically connected with the space transforming plate. | 02-05-2015 |
Patent application number | Description | Published |
20140306729 | POSITION ADJUSTABLE PROBING DEVICE AND PROBE CARD ASSEMBLY USING THE SAME - A position adjustable probing device adapted for being mounted to a circuit board includes a frame, a probe head, a space transformer module and an elevation adjusting structure. The frame has a first surface, a second surface opposite to the first surface, and a first opening penetrating through the first and second surfaces. The probe head is coupled to the frame. The space transformer module is disposed in the first opening. The elevation adjusting structure is provided at the frame and has a plurality of spacers for adjusting a position of the frame relative to a reference surface in a vertical direction. | 10-16-2014 |
20140306730 | ALIGNMENT ADJUSTING MECHANISM FOR PROBE CARD, POSITION ADJUSTING MODULE USING THE SAME AND MODULARIZED PROBING DEVICE - An alignment adjusting mechanism for a probe card includes a frame, a substrate and positioning screws. The frame has an opening, an inner periphery wall surrounding around the opening, and an outer periphery wall corresponding to the inner periphery wall. The substrate is disposed in the opening and supported by a support flange extending from the inner periphery wall toward a center of the opening. The frame is provided with a plurality of positioning threaded holes each extending from the outer periphery wall to the inner periphery wall in communication with the opening. Each positioning screw is threaded into one of the positioning threaded holes and has an end stopped at a lateral side of the substrate. By turning the positioning screws, the planimetric position of the substrate on an imaginary plane is adjustable. | 10-16-2014 |
20140352460 | Probe Needle and Probe Module Using the Same - A probe needle includes a head, a tail and a body connected between the head and the tail and provided with a first flat section curvedly extending from the head towards the tail for providing sufficient deformation when the tail is pressed on a device under test, and a second flat section neighbored to the first flat section for supporting the probe needle in between upper and lower dies. When the probe needles are used in a probe module, the probe needles can be arranged with a pitch same as that of the conventional probe needles even though the probe needles are formed from posts having a relatively greater diameter than that of the posts for making the conventional probe needles, such that the probe needles may have enhanced current withstanding capacity and prolonged lifespan. | 12-04-2014 |
20150033553 | ASSEMBLY METHOD OF DIRECT-DOCKING PROBING DEVICE - An assembly method of direct-docking probing device is provided. First, a space transforming plate made by back-end-of-line semiconductor manufacturing process is provided, so the thickness of the space transforming plate is predetermined by the client of probe card manufacturer. Then a reinforcing plate in which a plurality of circuits disposed is provided, which has larger mechanical strength than the space transforming plate. After that the reinforcing plate and the space transforming plate are joined and electrically connected by a plurality of solders so as to form a space transformer. Then, a conductive elastic member and a probe interface board are provided. Thereafter, the space transformer and the conductive elastic member are mounted on the probe interface board. After that, at least one vertical probe assembly having a plurality of vertical probes is mounted on the space transforming plate, and the vertical probes is electrically connected with the space transforming plate. | 02-05-2015 |
Patent application number | Description | Published |
20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 12-01-2011 |
20110312145 | SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-22-2011 |
20130130456 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region. | 05-23-2013 |
20130277750 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 10-24-2013 |
20130323891 | Integrated Circuit Device with Well Controlled Surface Proximity and Method of Manufacturing Same - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 12-05-2013 |
20140327086 | Semiconductor Device and Method for Forming Same - A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors. | 11-06-2014 |
20150035012 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 02-05-2015 |
Patent application number | Description | Published |
20100099262 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY CELL USING SELF-ALIGNED METAL SILICIDE - In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided. | 04-22-2010 |
20100171161 | DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved. | 07-08-2010 |
20100227460 | METHOD OF MANUFACTURING NOR FLASH MEMORY - In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided. | 09-09-2010 |
20100230738 | NOR FLASH MEMORY STRUCTURE WITH HIGHLY-DOPED DRAIN REGION AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole. | 09-16-2010 |
20140030860 | MANUFACTURING METHOD OF TUNNEL OXIDE OF NOR FLASH MEMORY - A manufacturing method of tunnel oxide of NOR flash memory controls the temperature and thickness of tunnel oxide in a gate structure to prevent a channel region to change its doping concentration and range due to a high-temperature manufacturing process, so as to overcome the leakage current and improve the reliability of storing data. | 01-30-2014 |
20140078832 | NON-VOLATILE MEMORY HAVING DISCRETE ISOLATION STRUCTURE AND SONOS MEMORY CELL, METHOD OF OPERATING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory. | 03-20-2014 |