Patent application number | Description | Published |
20080290468 | STRUCTURE OF FLEXIBLE ELECTRONICS AND OPTOELECTRONICS - A method for producing a flexible electronic device is provided. The method comprises steps of providing a flexible substrate, forming an inorganic film on the flexible substrate and etching the inorganic film to obtain an electronic element of the electronic device. In another aspect, a flexible electronic device is provided. The flexible electronic device comprises a flexible substrate and an inorganic film disposed on the flexible substrate and having an electronic element, wherein the electronic element is formed by etching the inorganic film. | 11-27-2008 |
20110032765 | Memory Formed By Using Defects - A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read. | 02-10-2011 |
20110053351 | Solar Cell Defect Passivation Method - The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency. | 03-03-2011 |
20110284074 | PHOTOVOLTAIC CELL - A photovoltaic cell includes a first type doped mono-crystalline silicon substrate, an intrinsic amorphous silicon layer, a second type doped amorphous silicon layer, a first type doped crystalline Ge-containing layer, and a pair of electrodes. The first type doped mono-crystalline silicon substrate has a front surface and a rear surface. The intrinsic amorphous silicon layer is disposed on the front surface. The second type doped amorphous silicon layer is disposed on the intrinsic amorphous silicon layer. The first type doped crystalline Ge-containing layer is disposed on the rear surface. The pair of electrodes are electrically connected to the second type doped amorphous silicon layer and first type doped crystalline Ge-containing layer, respectively. | 11-24-2011 |
20130089943 | METHOD OF MANUFACTURING A SOLAR CELL - An embodiment of the present disclosure provides method of manufacturing a solar cell. The method comprises the steps of providing a silicon substrate, forming a P-N junction structure in the silicon substrate, forming an oxide layer for passivating the surface defect of the substrate that has a low reflectivity for AM1.5G solar spectrum, and forming a plurality of metal electrodes on the silicon substrate. | 04-11-2013 |
20130221534 | Through Silicon Via Layout Pattern - A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape. | 08-29-2013 |
20140124774 | MOSFET DEVICE - A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction. | 05-08-2014 |
Patent application number | Description | Published |
20080217651 | Photodetector - A photodetector is provided. The photodetector includes a base piece; a germanium layer mounted on the base piece and including a first area and a second area; a first metal electrode mounted on the first area; an insulation layer mounted on the second area; and a second metal electrode mounted on the insulation layer. | 09-11-2008 |
20080298410 | LASER APPARATUS AND THE MANUFACTURING METHOD THEREOF - A laser apparatus is provided. The laser apparatus includes at least one semiconductor layer having a first surface and a second surface and an insulator layer formed on the first surface of the at least one semiconductor layer, wherein the at least one semiconductor layer and the insulator form a laser cavity. | 12-04-2008 |
20090008736 | METHOD FOR PHOTO-DETECTING AND APPARATUS FOR THE SAME - A method for photo-detecting and an apparatus for the same are provided. The apparatus for photo-detecting includes a first P-N diode and a second P-N diode. The first P-N diode, has a first P-N junction which has a first thickness, by which a first electrical signal is generated when irradiated by light, and the second P-N diode has a second P-N junction which has a second thickness, by which a second electrical signal is generated when irradiated by light. The second thickness is larger than the first thickness and an operation of the first electrical signal and the second electrical signal is proceeded for obtaining a third electrical signal. | 01-08-2009 |
20090194152 | THIN-FILM SOLAR CELL HAVING HETERO-JUNCTION OF SEMICONDUCTOR AND METHOD FOR FABRICATING THE SAME - A thin-film solar cell having a hetero-junction of semiconductor and the fabrication method thereof are provided. Instead of the conventional hetero-junction of III-V semiconductor or homo-structure of IV semiconductor, the thin-film solar cell according to the present invention adopts a novel hetero-junction structure of IV semiconductor to improve the cell efficiency thereof. By adjusting the amount of layer sequences and the thickness of the hetero-junction structure, the cell efficiency of the thin-film solar cell according to the present invention is also optimized. | 08-06-2009 |
20100024870 | Structure And Method Of Solar Cell Efficiency Improvement By Strain Technology - A structure and a method of the solar cell efficiency improvement by the strain technology are provided. The solar cell has a first surface and a second surfaces which at least a gasket is disposed thereon for supporting the solar cell and being the axle whiling stressing. The method includes the steps of: (a) applying at least a stress on the first surface; (b) generating a supporting force on the second surface; and (c) generating at least a strain in the solar cell. In addition, the present invention also includes a method involving a step of: (a) applying a mechanical stress to the solar cell; (b) generating a tension in the solar cell by at least two materials having different lattice constants; or (c) generating another tension in the solar cell by a shallow trench isolation filler, a high tensile/compressive stress silicon nitride layer and a combination thereof. | 02-04-2010 |
20120024366 | Thin film solar cell structure and fabricating method thereof - A thin film solar cell structure and the fabricating method thereof are disclosed. A passivation layer is embedded into the thin film solar cell structure to be in contact with an absorbing layer. The interface trap density of the absorbing layer is reduced by the surface electric field of the passivation layer. The invention helps improve the power conversion efficiency and protect the absorbing layer. | 02-02-2012 |
20130087191 | POINT-CONTACT SOLAR CELL STRUCTURE - A point-contact solar cell structure includes a semiconductor substrate, a front electrode, a first passivation layer, a second passivation layer, and a rear electrode. The semiconductor substrate includes an upper surface, a lower surface, and an emitter layer, a base layer, and a plurality of locally doped regions located between the upper surface and the lower surface. The plurality of locally doped regions is located on the lower surface at intervals. The second passivation layer is located on the lower surface, and has a plurality of openings disposed respectively corresponding to the locally doped regions. The rear electrode is located on one side of the second passivation layer opposite to the semiconductor substrate, and passes through the second passivation layer via the openings to contact the locally doped regions. The width of at least one opening corresponding to the front electrode is greater than that of the remaining openings. | 04-11-2013 |
20130168696 | Silicon Carbide Schottky Diode Device with Mesa Termination and Manufacturing Method Thereof - A silicon carbide Schottky diode device with mesa terminations and the manufacturing method thereof are provided. The silicon carbide Schottky diode device includes an n-type epitaxial silicon carbide layer with mesa terminations on an n-type silicon carbide substrate, two p-type regions in the n-type epitaxial silicon carbide layer and a Schottky metal contact on the n-type epitaxial silicon carbide layer and the p-type regions, a dielectric layer on sidewalls and planes of the mesa terminations. | 07-04-2013 |
20140008726 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface. | 01-09-2014 |
Patent application number | Description | Published |
20090302349 | STRAINED GERMANIUM FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - A strained germanium field effect transistor (FET) and method of fabricating the same is related to the strained Ge field effect transistor with a thin and pure Ge layer as a carrier channel. The pure Ge layer with the thickness between 1 nm and 10 nm is formed between an unstrained substrate and a gate insulation layer, and directly contacts with the unstrained substrate. The gate is disposed on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained Ge FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. Furthermore, a Si protective layer with extremely thin thickness can be deposed between and directly contacts with the gate insulation layer and the pure Ge layer. | 12-10-2009 |
20140131768 | BRIDGE STRUCTURE - A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block. | 05-15-2014 |
20140264439 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a substrate, at least a first N-type germanium (Ge) structure and at least a first P-type Ge structure. The first N-type Ge structure is formed on the substrate and has two end parts and at least a first central part bonded between the two end parts thereof. The first central part is floated over the substrate, and a side surface of the first central part is a {111} Ge crystallographic surface. The first P-type Ge structure is formed on the substrate and has two end parts and at least a second central part bonded between the two end parts thereof. The side surface of the second central part is a {110} Ge crystallographic surface. | 09-18-2014 |
20140374834 | GERMANIUM STRUCTURE, GERMANIUM FIN FIELD EFFECT TRANSISTOR STRUCTURE AND GERMANIUM COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR STRUCTURE - A germanium (Ge) structure includes a substrate, a Ge layer and at least a Ge spatial structure. The Ge layer is formed on the substrate, and a surface of the Ge layer is a Ge {110} lattice plane. The Ge spatial structure is formed in the Ge layer and includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. Because Ge {111} surface channels have very high electron mobility, this Ge spatial structure may be applied for fabricating high-performance Ge semiconductor devices. | 12-25-2014 |