| Patent application number | Description | Published |
|---|
| 20090096484 | LEVEL SHIFTERS - Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal. | 04-16-2009 |
| 20090166849 | SEMICONDUCTOR CHIP - A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member. | 07-02-2009 |
| 20090184395 | INPUT/OUTPUT (I/O) BUFFER - An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value. | 07-23-2009 |
| 20090187874 | CIRCUIT AND CIRCUIT DESIGN METHOD - A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path. | 07-23-2009 |
| 20090294977 | SEMICONDUCTOR DIE AND BOND PAD ARRANGEMENT METHOD THEREOF - A bond pad arrangement method of a semiconductor die is provided. The bond pad arrangement method includes: determining a bond pad architecture including a plurality of bond pads at a peripheral region of the semiconductor die, where each of the bond pads is defined to have a predetermined connection region; controlling an orientation of each bond pad at the peripheral region of the semiconductor die, thereby selectively configuring the predetermined connection region thereof to be electrically connected to one of a plurality of conductive structures included in at least one metal interconnect layer of the semiconductor die; and storing a bond pad design of the bond pads at the peripheral region of the semiconductor die. | 12-03-2009 |
| 20100117207 | BOND PAD ARRAY FOR COMPLEX IC - An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers. | 05-13-2010 |
| 20100171211 | SEMICONDUCTOR DEVICE - A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost. | 07-08-2010 |
| 20100328987 | E-FUSE APPARATUS FOR CONTROLLING REFERENCE VOLTAGE REQUIRED FOR PROGRAMMING/READING E-FUSE MACRO IN AN INTEGRATED CIRCUIT VIA SWITCH DEVICE IN THE SAME INTEGRATED CIRCUIT - An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode. | 12-30-2010 |
