| Patent application number | Description | Published |
|---|
| 20090134471 | SEMICONDUCTOR INTERCONNECT - One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed. | 05-28-2009 |
| 20090258471 | Application of Different Isolation Schemes for Logic and Embedded Memory - The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic. | 10-15-2009 |
| 20100163997 | EPITAXIAL DEPOSITION-BASED PROCESSES FOR REDUCING GATE DIELECTRIC THINNING AT TRENCH EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed. | 07-01-2010 |
| 20100164004 | METHODS FOR REDUCING GATE DIELECTRIC THINNING ON TRENCH ISOLATION EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed. | 07-01-2010 |
| 20100274506 | METHOD FOR MEASURING INTERFACE TRAPS IN THIN GATE OXIDE MOSFETS - A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points. | 10-28-2010 |
| Patent application number | Description | Published |
|---|
| 20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 12-04-2008 |
| 20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 12-04-2008 |
| 20090166888 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 07-02-2009 |
| 20090170246 | FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION - A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer. | 07-02-2009 |
| 20090176366 | MICROPAD FORMATION FOR A SEMICONDUCTOR - A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips. | 07-09-2009 |
| 20090191708 | METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT - A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields. | 07-30-2009 |
| 20100327440 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 12-30-2010 |
| 20110151663 | METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 06-23-2011 |
| Patent application number | Description | Published |
|---|
| 20120038786 | Decreasing Image Acquisition Time for Compressive Imaging Devices - Mechanisms for increasing the rate of acquisition of compressed/encoded image representations are disclosed. An imaging system may deliver subsets of a modulated light stream onto respective light sensing devices. The light sensing devices may be sampled in parallel. Samples from each light sensing device may be used to construct a respective sub-image of a final image. The parallelism allows compressed images to be acquired at a higher rate. The number of light sensing devices and/or the number of pixels per image may be selected to achieve a target image acquisition rate. In another embodiment, spatial portions of the incident light stream are separated and delivered to separate light modulators. In yet another embodiment, the incident light stream is split into a plurality of beams, each of which retains the image present in the incident light stream and is delivered to a separate light modulator. | 02-16-2012 |
| 20120038789 | Determining Light Level Variation in Compressive Imaging by Injecting Calibration Patterns into Pattern Sequence - An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation. | 02-16-2012 |
| 20120038790 | Low-Pass Filtering of Compressive Imaging Measurements to Infer Light Level Variation - An imaging system and method that captures compressive sensing (CS) measurements of a received light stream, and also obtains samples of background light level (BGLL). The BGLL samples may be used to compensate the CS measurements for variations in the BGLL. The system includes: a light modulator to spatially modulate the received light stream with spatial patterns, and a lens to concentrate the modulated light stream onto a light detector. The samples of BGLL may be obtained in various ways: (a) injecting calibration patterns among the spatial patterns; (b) measuring complementary light reflected by digital micromirrors onto a secondary output path; (c) separating and measuring a portion of light from the optical input path; (d) low-pass filtering the CS measurements; and (e) employing a light power meter with its own separate input path. Also, the CS measurements may be high-pass filtered to attenuate background light variation. | 02-16-2012 |
| 20120038819 | TIR Prism to Separate Incident Light and Modulated Light in Compressive Imaging Device - A compressive imaging system including a light modulator, a light sensing device and a TIR prism. The TIR prism is configured to receive an incident light beam, to provide the incident light beam to the light modulator, to receive a modulated light beam MLB from the light modulator, and to direct the modulated light beam onto a sensing path. The light sensing device receives the modulated light beam (or at least a portion of the modulated light beam) and generates an electrical signal that represents intensity of the modulated light beam (or the “at least a portion” of the modulated light beam). The TIR prism may reduce a distance required to separate the incident light beam from the modulated light beam. | 02-16-2012 |
