| Patent application number | Description | Published |
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| 20080215923 | DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) - Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events. | 09-04-2008 |
| 20080282015 | DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols. | 11-13-2008 |
| 20080307147 | COMPUTER SYSTEM BUS BRIDGE - A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module. | 12-11-2008 |
| 20090024859 | STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS - A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available. | 01-22-2009 |
| 20090024862 | STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS - A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source. | 01-22-2009 |
| 20090044054 | DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS - Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. | 02-12-2009 |
| 20090044160 | DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS - Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides. | 02-12-2009 |
| 20090091351 | CHIP IDENTIFICATION SYSTEM AND METHOD - Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
| 20090094566 | DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM - Disclosed is a design structure for an on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
| 20090132732 | UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
| 20090132747 | STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
| 20090153324 | DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT - An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. | 06-18-2009 |
| 20090157334 | MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT - An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal. | 06-18-2009 |
| 20090268541 | DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded. | 10-29-2009 |
