| Patent application number | Description | Published |
|---|
| 20080231484 | Variable sized aperture window of an analog-to-digital converter - An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems. | 09-25-2008 |
| 20080231489 | Analog-to-digital converter system with increased sampling frequency - The present invention is an improvement in sampling a high frequency input analog signal and converting it to a digital output signal. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier. | 09-25-2008 |
| 20080282062 | Method and apparatus for loading data and instructions into a computer - A computer array ( | 11-13-2008 |
| 20090083360 | Shift-add based parallel multiplication - A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count. | 03-26-2009 |
| 20090083361 | Shift-add based multiplication - A system for multiplication of multi-bit first and second values. A processor is provided that has first and second memories with bit-positions that can all be zero or one and where the first memory has a low bit (LB). The first value is arranged in the first memory so its LSB is in the first memory LB, and the remaining bit-positions in the first memory are set to zero. The second value is arranged in the second memory such that its LSB is in the bit-position of the second memory that is next higher in order than the MSB of the first value in the first memory, and the remaining bit-positions in the second memory are set to zero. A +* operation is then performed a quantity of times equaling the number of significant bits in the first value, inclusive, thus obtaining the product of the first and second values. | 03-26-2009 |
| 20090083507 | Shift-add mechanism - A method to perform a shift-add operation on two values loaded in two memories of a processor where the first memory has a low bit (LB) and a high bit (HB). If the LB is zero, then this is case ( | 03-26-2009 |
| 20090257263 | Method and Apparatus for Computer Memory - A method and apparatus for forming computer memory | 10-15-2009 |
| 20090259770 | Method and Apparatus for Serializing and Deserializing - A method and apparatus for serialization of a transmitted data stream and deserialization of data on a single die chip | 10-15-2009 |
| 20090259826 | Microprocessor Extended Instruction Set Mode - Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions. | 10-15-2009 |
| 20090259892 | Method and Apparatus for Producing a Metastable Flip Flop - The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus | 10-15-2009 |
| 20090262255 | Method and apparatus for remote control of audio visual systems - The invention provides a method for improving the functionality of the jump button associated with television, cable/satellite receiver, or any other multi-channel device controlling remote control. The apparatus provides a jump button with the ability to access a wide variety of channels in an intelligent manner. At present, the jump button has the functionality such that the jump to location associated with selecting the jump button is the previously viewed channel, regardless of how the current channel being viewed is selected. The invention disclosed herein is a method of performing jumps on a device like a remote control in a more useful manner. | 10-22-2009 |
| 20090265524 | Method and apparatus for arranging multiple processors on a semiconductor chip - A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses. | 10-22-2009 |
| 20090300334 | Method and Apparatus for Loading Data and Instructions Into a Computer - A computer array ( | 12-03-2009 |
| 20100023733 | Microprocessor Extended Instruction Set Precision Mode - A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction. | 01-28-2010 |
| 20100064118 | Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups - A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated. | 03-11-2010 |
| 20100117880 | Variable sized aperture window of an analog-to-digital converter - An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems. | 05-13-2010 |
| 20100123570 | Localized Control Method and Apparatus - A zoned interactive control area ( | 05-20-2010 |
| 20100125440 | Method and Apparatus for Circuit Simulation - A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one-dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached. | 05-20-2010 |
| 20100125441 | Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete. | 05-20-2010 |
| 20100138207 | Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete. | 06-03-2010 |
| 20100254197 | Latch Pulse Delay Control - A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch. | 10-07-2010 |
| 20100281238 | Execution of instructions directly from input source - A computer array ( | 11-04-2010 |
| 20100325389 | Microprocessor communications system - A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to save and retrieve data and/or instructions from memory. A stack register selector contains a plurality of stack registers and a plurality of shift registers, which are interconnected. The stack registers are selected by the shift registers in such a way that the stack registers operate in a circular repeating pattern, which prevents overflow and underflow of stacks. | 12-23-2010 |
| 20110013467 | System and Method for Reading Memory - A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die. | 01-20-2011 |
